Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	`timescale 1ns / 1ps
2	module uart_peripheral(clk, sram_data, addr, nwe, ncs, noe, reset, led, RxD,TxD,irq_pin);
3	parameter B = (7);
4
5	input clk, nwe, ncs, noe, reset,RxD;
6	input [2:0] addr;
7	inout [B:0] sram_data;
8	output led,TxD;
9	output irq_pin;
10
11	// synchronize signals
12	reg sncs, snwe;
13	reg [2:0] buffer_addr;
14	reg [B:0] buffer_data;
15	reg [24:0] counter;
16	// interfaz fpga signals
17	// wire [12:0] addr;
18
19	// bram interfaz signals
20	reg we;
21	reg w_st;
22	wire [7:0] RD;
23	reg [B:0] wdBus;
24	wire [B:0] rdBus;
25
26	// interefaz signals assignments
27	wire T = ~noe \| ncs;
28	assign sram_data = T?8'bZ:rdBus;
29
30	//--------------------------------------------------------------------------
31
32	// synchronize assignment
33	always @(negedge clk)
34	begin
35	sncs <= ncs;
36	snwe <= nwe;
37	buffer_data <= sram_data;
38	buffer_addr <= addr;
39	end
40
41	// write access cpu to bram
42	always @(posedge clk)
43	if(~reset) {w_st, we, wdBus} <= 0;
44	else begin
45	wdBus <= buffer_data;
46	case (w_st)
47	0: begin
48	we <= 0;
49	if(sncs \| snwe) w_st <= 1;
50	end
51	1: begin
52	if(~(sncs \| snwe)) begin
53	we <= 1;
54	w_st <= 0;
55	end
56	else we <= 0;
57	end
58	endcase
59	end
60
61
62
63	//the UART Module
64	UART UART(
65	.CLK(clk),
66	.reset(~reset),
67	.CS(~sncs),
68	.nRW(we),
69	.data_in(wdBus),
70	.data_out(rdBus),
71	.RxD(RxD),
72	.TxD(TxD),
73	.add(buffer_addr),
74	.nIRQ(irq_pin)
75	);
76
77
78	always @(posedge clk) begin
79	if (~reset)
80	counter <= {25{1'b0}};
81	else
82	counter <= counter + 1;
83	end
84	assign led = counter[24];
85
86
87	endmodule
88

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