Hardware Design: SIE
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| 1 | #include <stdio.h> |
| 2 | #include <unistd.h> |
| 3 | |
| 4 | #include "jz47xx_gpio.h" |
| 5 | #include "jz47xx_mmap.h" |
| 6 | |
| 7 | #define CS2_PORT JZ_GPIO_PORT_B |
| 8 | #define CS2_PIN 26 |
| 9 | #define RHR 0x00 /* Receive Holding Register */ |
| 10 | #define THR 0x00 /* Receive Holding Register */ |
| 11 | #define IER 0x01 /* Interrupt Enable Register */ |
| 12 | #define FCR 0x02 /* FIFO control Register */ |
| 13 | #define ISR 0x02 /* Interrupt Status Register */ |
| 14 | #define LCR 0x03 /* Line control register */ |
| 15 | #define MCR 0x04 /* Modem Control Register */ |
| 16 | #define LSR 0x05 /* Line Status Register */ |
| 17 | #define MSR 0x06 /* Modem Status Register */ |
| 18 | #define SCR 0x07 /* Scratch pad Register */ |
| 19 | /* This two offsets are used for defining the baud rate */ |
| 20 | #define DIVLSB 0x00 /* Divisor LSB latch address */ |
| 21 | #define DIVMSB 0x01 /* Divisor MSB Latch address */ |
| 22 | |
| 23 | |
| 24 | |
| 25 | #include <stdio.h> |
| 26 | #include <unistd.h> |
| 27 | |
| 28 | #include "jz47xx_gpio.h" |
| 29 | #include "jz47xx_mmap.h" |
| 30 | |
| 31 | #define CS2_PORT JZ_GPIO_PORT_B |
| 32 | #define CS2_PIN 26 |
| 33 | #define RHR 0x00 /* Receive Holding Register */ |
| 34 | #define THR 0x00 /* Receive Holding Register */ |
| 35 | #define IER 0x01 /* Interrupt Enable Register */ |
| 36 | #define FCR 0x02 /* FIFO control Register */ |
| 37 | #define ISR 0x02 /* Interrupt Status Register */ |
| 38 | #define LCR 0x03 /* Line control register */ |
| 39 | #define MCR 0x04 /* Modem Control Register */ |
| 40 | #define LSR 0x05 /* Line Status Register */ |
| 41 | #define MSR 0x06 /* Modem Status Register */ |
| 42 | #define SCR 0x07 /* Scratch pad Register */ |
| 43 | /* This two offsets are used for defining the baud rate */ |
| 44 | #define DIVLSB 0x00 /* Divisor LSB latch address */ |
| 45 | #define DIVMSB 0x01 /* Divisor MSB Latch address */ |
| 46 | |
| 47 | |
| 48 | int main () { |
| 49 | |
| 50 | JZ_PIO *pio; |
| 51 | char *virt_addr, get_tecla, in, in2=0, in1=0; |
| 52 | int i; |
| 53 | pio = jz_gpio_map (CS2_PORT); |
| 54 | jz_gpio_as_func (pio, CS2_PIN, 0); |
| 55 | |
| 56 | virt_addr = (int *) jz_mmap (0x13010000) + 0x18; |
| 57 | if (*virt_addr != 0xFFF7700) |
| 58 | { // 0 WS, 8 bits |
| 59 | *virt_addr = 0xFFF7700; |
| 60 | // printf ("Configuring CS2 8 bits \n"); |
| 61 | } |
| 62 | else |
| 63 | printf ("CS3, already configured\n"); |
| 64 | |
| 65 | virt_addr = (JZ_REG *) jz_mmap (0x15000000); |
| 66 | |
| 67 | virt_addr[LCR]=0x80;//registros de configuracion de UART |
| 68 | virt_addr[DIVMSB]=0x00; |
| 69 | virt_addr[DIVLSB]=0x0C; |
| 70 | virt_addr[LCR]=0x03; |
| 71 | virt_addr[IER]= 0x01; |
| 72 | |
| 73 | |
| 74 | |
| 75 | |
| 76 | |
| 77 | virt_addr[THR]=0x0f;//inicio de estados |
| 78 | usleep(20000); |
| 79 | virt_addr[THR]=0x0E; |
| 80 | usleep(20000); |
| 81 | virt_addr[THR]=0x01; |
| 82 | usleep(20000); |
| 83 | virt_addr[THR]=0x01; |
| 84 | usleep(20000); |
| 85 | for (i=0;i<48;i++)//registros de configuracion |
| 86 | {virt_addr[THR]=0x28; |
| 87 | usleep(20000);} |
| 88 | for (i=0;i<48;i++) |
| 89 | {virt_addr[THR]=0x4A; |
| 90 | usleep(20000);} |
| 91 | for (i=0;i<48;i++) |
| 92 | {virt_addr[THR]=0x52; |
| 93 | usleep(20000);} |
| 94 | for (i=0;i<48;i++) |
| 95 | {virt_addr[THR]=0x14; |
| 96 | usleep(20000);} |
| 97 | for (i=0;i<48;i++) |
| 98 | {virt_addr[THR]=0xA6; |
| 99 | usleep(20000);} |
| 100 | virt_addr[THR]=0x11; |
| 101 | usleep(20000); |
| 102 | virt_addr[THR]=0x00; |
| 103 | usleep(20000); |
| 104 | virt_addr[THR]=0x64; |
| 105 | usleep(20000); |
| 106 | virt_addr[THR]=0x00; |
| 107 | usleep(20000); |
| 108 | virt_addr[THR]=0x6c; |
| 109 | usleep(20000); |
| 110 | virt_addr[THR]=0x00; |
| 111 | usleep(20000); |
| 112 | virt_addr[THR]=0x00;//fin de registros de configuracion |
| 113 | usleep(20000); |
| 114 | virt_addr[THR]=0x04; |
| 115 | usleep(20000); |
| 116 | virt_addr[THR]=0x04; |
| 117 | usleep(20000); |
| 118 | virt_addr[THR]=0x0f; |
| 119 | usleep(20000); |
| 120 | virt_addr[THR]=0x0e;//fin de estados finitos |
| 121 | |
| 122 | |
| 123 | |
| 124 | while (1){ |
| 125 | |
| 126 | //recepcion de los registros enviados por el integrado |
| 127 | |
| 128 | virt_addr[THR]=0x06; |
| 129 | in=virt_addr[THR]; |
| 130 | usleep(120000); |
| 131 | |
| 132 | |
| 133 | |
| 134 | |
| 135 | |
| 136 | |
| 137 | } |
| 138 | |
| 139 | |
| 140 | |
| 141 | |
| 142 | } |
| 143 |
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