Root/lm32/logic/sakc/Makefile

1VINCDIR= \
2    -I../rtl/wb_conbus \
3    -I../rtl/lm32 \
4    -I../rtl/wb_ddr
5
6SYN_SRC=
7
8SIM_SRC= \
9    system_tb.v \
10    ../sim/sram/sram16.v \
11    ../sim/unisims/BUFG.v \
12    ../sim/unisims/DCM.v
13
14SRC= \
15    ../system.v \
16    ../rtl/lac/lac.v \
17    ../rtl/lac/uart.v \
18    ../rtl/lac/dp_ram.v \
19    ../rtl/lm32/lm32_cpu.v \
20    ../rtl/lm32/lm32_instruction_unit.v \
21    ../rtl/lm32/lm32_decoder.v \
22    ../rtl/lm32/lm32_simtrace.v \
23    ../rtl/lm32/lm32_load_store_unit.v \
24    ../rtl/lm32/lm32_adder.v \
25    ../rtl/lm32/lm32_addsub.v \
26    ../rtl/lm32/lm32_logic_op.v \
27    ../rtl/lm32/lm32_shifter.v \
28    ../rtl/lm32/lm32_multiplier.v \
29    ../rtl/lm32/lm32_mc_arithmetic.v \
30    ../rtl/lm32/lm32_interrupt.v \
31    ../rtl/lm32/lm32_icache.v \
32    ../rtl/lm32/lm32_dcache.v \
33    ../rtl/lm32/lm32_ram.v \
34    ../rtl/wb_bram/wb_bram.v \
35    ../rtl/wb_uart/wb_uart.v \
36    ../rtl/wb_timer/wb_timer.v \
37    ../rtl/wb_gpio/wb_gpio.v \
38    ../rtl/wb_conbus/wb_conbus_top.v \
39    ../rtl/wb_conbus/wb_conbus_arb.v \
40    ../rtl/wb_sram/wb_sram32.v
41
42#############################################################################
43# Synthesis constants
44SYNCLEAN=system.bgn system.drc system.mrp system.ngd system.pcf
45SYNCLEAN+=system.bld system.lso system.ncd system.ngm system.srp
46SYNCLEAN+=system.bit system_signalbrowser.* system-routed_pad.tx
47SYNCLEAN+=system.map system_summary.xml timing.twr
48SYNCLEAN+=system-routed* system_usage* system.ngc param.opt netlist.lst
49SYNCLEAN+=xst system.prj *ngr *xrpt _xmsgs xlnx_auto_0_xdb *html *log *xwbt
50
51USAGE_DEPTH=0
52SMARTGUIDE=
53
54#############################################################################
55# Simulation constants
56SIMCLEAN=system_tb.vvp system_tb.vcd verilog.log system_tb.vvp.list simulation
57
58CVER=cver
59GTKWAVE=gtkwave
60IVERILOG=iverilog
61VVP=vvp
62    
63#############################################################################
64#
65sim: system_tb.vcd
66syn: system.bit
67view: system_tb.view
68
69#############################################################################
70# Ikarus verilog simulation
71
72system_tb.vvp:
73    rm -rf simulation && mkdir simulation
74    cp system_tb.v system_conf.v simulation && cd simulation && rm -f $@.list
75    for i in $(SRC); do echo $$i >> simulation/$@.list; done
76    for i in $(SIM_SRC); do echo $$i >> simulation/$@.list; done
77    cd simulation && $(IVERILOG) -o $@ $(VINCDIR) -c $@.list -s $(@:.vvp=)
78
79%.vcd: %.vvp
80    cd simulation && $(VVP) $<
81
82#############################################################################
83# ISE Synthesis
84
85
86system.prj:
87    rm -rf build && mkdir build
88    @rm -f $@
89    for i in $(SRC); do echo verilog work $$i >> build/$@; done
90    for i in $(SRC_HDL); do echo VHDL work $$i >> build/$@; done
91
92system.ngc: system.prj
93    cd build && xst -ifn ../system.xst
94
95system.ngd: system.ngc system.ucf
96    cd build && ngdbuild -uc ../system.ucf system.ngc
97
98system.ncd: system.ngd
99    cd build && map $(SMARTGUIDE) system.ngd
100
101system-routed.ncd: system.ncd
102    cd build && par $(SMARTGUIDE) -ol high -w system.ncd system-routed.ncd
103
104system.bit: system-routed.ncd
105    cd build && bitgen -w system-routed.ncd system.bit
106    @mv -f build/system.bit $@
107
108system.mcs: system.bit
109    cd build && promgen -u 0 system
110
111system-routed.xdl: system-routed.ncd
112    cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
113
114system-routed.twr: system-routed.ncd
115    cd build && trce -v 10 system-routed.ncd system.pcf
116
117timing: system-routed.twr
118
119usage: system-routed.xdl
120    xdlanalyze.pl system-routed.xdl $(USAGE_DEPTH)
121
122####################################################################
123# final targets
124
125%.view: %.vcd
126    cd simulation && $(GTKWAVE) $< $<.save
127
128clean:
129    rm -Rf build $(SYNCLEAN) $(SIMCLEAN)
130
131.PHONY: clean view
132

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