Root/lm32/logic/sakc/cores/uart/doc/uart.tex

1\documentclass[a4paper,11pt]{article}
2\usepackage{fullpage}
3\usepackage[latin1]{inputenc}
4\usepackage[T1]{fontenc}
5\usepackage[normalem]{ulem}
6\usepackage[english]{babel}
7\usepackage{listings,babel}
8\lstset{breaklines=true,basicstyle=\ttfamily}
9\usepackage{graphicx}
10\usepackage{moreverb}
11\usepackage{amsmath}
12\usepackage{url}
13\usepackage{tabularx}
14
15\title{Simple UART}
16\author{S\'ebastien Bourdeauducq}
17\date{December 2009}
18\begin{document}
19\setlength{\parindent}{0pt}
20\setlength{\parskip}{5pt}
21\maketitle{}
22\section{Specifications}
23The UART is based on a very simple design from Das Labor. Its purpose is basically to provide a debug console.
24
25The UART operates with 8 bits per character, no parity, and 1 stop bit. The default baudrate is configured during synthesis and can be modified at runtime using the divisor register.
26
27The divisor is computed as follows :
28\begin{equation*}
29\text{divisor} = \frac{\text{Clock frequency (Hz)}}{16 \cdot \text{Bitrate (bps)}}
30\end{equation*}
31
32\section{Registers}
33\begin{tabularx}{\textwidth}{|l|l|l|X|}
34\hline
35\bf{Offset} & \bf{Read/Write} & \bf{Default} & \bf{Description} \\
36\hline
370x0 & RW & 0x00 & Data register. Received bytes and bytes to transmit are read/written from/to this register. \\
38\hline
390x4 & RW & for default bitrate & Divisor register (for bitrate selection). \\
40\hline
41\end{tabularx}\\
42
43\section{Interrupts}
44The core has two active-high edge-sensitive interrupts outputs.
45
46The ``RX'' interrupt is sent whenever a new character is received. The CPU should then read the data register immediately. If a new character is sent before the CPU has had time to read it, the first character will be lost.
47
48The ``TX'' interrupt is sent as soon as the UART finished transmitting a character. When the CPU has written to the data register, it must wait for the interrupt before writing again.
49
50\section{Using the core}
51Connect the CSR signals and the interrupts to the system bus and the interrupt controller. The \verb!uart_txd! and \verb!uart_rxd! signals should go to the FPGA pads. You must also provide the desired default baudrate and the system clock frequency in Hz using the parameters.
52
53\section*{Copyright notice}
54Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
55Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
56
57\end{document}
58

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