Hardware Design: SIE
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| 1 | /* |
| 2 | * Milkymist VJ SoC |
| 3 | * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq |
| 4 | * |
| 5 | * This program is free software: you can redistribute it and/or modify |
| 6 | * it under the terms of the GNU General Public License as published by |
| 7 | * the Free Software Foundation, version 3 of the License. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, |
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | * GNU General Public License for more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License |
| 15 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | /* FIXME: this module does not work. Find out why. */ |
| 19 | |
| 20 | module vgafb_asfifo #( |
| 21 | /* NB: those are fixed in this implementation */ |
| 22 | parameter DATA_WIDTH = 18, |
| 23 | parameter ADDRESS_WIDTH = 11 |
| 24 | ) ( |
| 25 | /* Reading port */ |
| 26 | output [17:0] Data_out, |
| 27 | output Empty_out, |
| 28 | input ReadEn_in, |
| 29 | input RClk, |
| 30 | |
| 31 | /* Writing port */ |
| 32 | input [17:0] Data_in, |
| 33 | output Full_out, |
| 34 | input WriteEn_in, |
| 35 | input WClk, |
| 36 | |
| 37 | input Clear_in |
| 38 | ); |
| 39 | |
| 40 | wire full; |
| 41 | wire empty; |
| 42 | |
| 43 | FIFO16 #( |
| 44 | .DATA_WIDTH(9), |
| 45 | .FIRST_WORD_FALL_THROUGH("TRUE") |
| 46 | ) fifo_lo ( |
| 47 | .ALMOSTEMPTY(), |
| 48 | .ALMOSTFULL(), |
| 49 | .DO(Data_out[7:0]), |
| 50 | .DOP(Data_out[8]), |
| 51 | .EMPTY(empty), |
| 52 | .FULL(full), |
| 53 | .RDCOUNT(), |
| 54 | .RDERR(), |
| 55 | .WRCOUNT(), |
| 56 | .WRERR(), |
| 57 | .DI(Data_in[7:0]), |
| 58 | .DIP(Data_in[8]), |
| 59 | .RDCLK(RClk), |
| 60 | .RDEN(ReadEn_in & ~empty & ~Clear_in), |
| 61 | .RST(Clear_in), |
| 62 | .WRCLK(WClk), |
| 63 | .WREN(WriteEn_in & ~full & ~Clear_in) |
| 64 | ); |
| 65 | |
| 66 | assign Empty_out = empty; |
| 67 | assign Full_out = full; |
| 68 | |
| 69 | FIFO16 #( |
| 70 | .DATA_WIDTH(9), |
| 71 | .FIRST_WORD_FALL_THROUGH("TRUE") |
| 72 | ) fifo_hi ( |
| 73 | .ALMOSTEMPTY(), |
| 74 | .ALMOSTFULL(), |
| 75 | .DO(Data_out[16:9]), |
| 76 | .DOP(Data_out[17]), |
| 77 | .EMPTY(), |
| 78 | .FULL(), |
| 79 | .RDCOUNT(), |
| 80 | .RDERR(), |
| 81 | .WRCOUNT(), |
| 82 | .WRERR(), |
| 83 | .DI(Data_in[16:9]), |
| 84 | .DIP(Data_in[17]), |
| 85 | .RDCLK(RClk), |
| 86 | .RDEN(ReadEn_in & ~empty & ~Clear_in), |
| 87 | .RST(Clear_in), |
| 88 | .WRCLK(WClk), |
| 89 | .WREN(WriteEn_in & ~full & ~Clear_in) |
| 90 | ); |
| 91 | |
| 92 | endmodule |
| 93 | |
| 94 |
Branches:
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