Root/lm32/logic/sakc/cores/vgafb/rtl/vgafb_ctlif.v

1/*
2 * Milkymist VJ SoC
3 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, version 3 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18module vgafb_ctlif #(
19    parameter csr_addr = 4'h0,
20    parameter fml_depth = 26
21) (
22    input sys_clk,
23    input sys_rst,
24    
25    input [13:0] csr_a,
26    input csr_we,
27    input [31:0] csr_di,
28    output reg [31:0] csr_do,
29    
30    output reg vga_rst,
31    
32    output reg [10:0] hres,
33    output reg [10:0] hsync_start,
34    output reg [10:0] hsync_end,
35    output reg [10:0] hscan,
36    
37    output reg [10:0] vres,
38    output reg [10:0] vsync_start,
39    output reg [10:0] vsync_end,
40    output reg [10:0] vscan,
41    
42    output reg [fml_depth-1:0] baseaddress,
43    input baseaddress_ack,
44    
45    output reg [17:0] nbursts,
46
47    output reg [1:0] vga_clk_sel
48);
49
50reg [fml_depth-1:0] baseaddress_act;
51
52always @(posedge sys_clk) begin
53    if(sys_rst)
54        baseaddress_act <= {fml_depth{1'b0}};
55    else if(baseaddress_ack)
56        baseaddress_act <= baseaddress;
57end
58
59wire csr_selected = csr_a[13:10] == csr_addr;
60
61always @(posedge sys_clk) begin
62    if(sys_rst) begin
63        csr_do <= 32'd0;
64        
65        vga_rst <= 1'b1;
66        
67        hres <= 10'd640;
68        hsync_start <= 10'd656;
69        hsync_end <= 10'd752;
70        hscan <= 10'd799;
71        
72        vres <= 10'd480;
73        vsync_start <= 10'd491;
74        vsync_end <= 10'd493;
75        vscan <= 10'd523;
76        
77        baseaddress <= {fml_depth{1'b0}};
78        
79        nbursts <= 18'd19200;
80        vga_clk_sel <= 2'd00;
81    end else begin
82        csr_do <= 32'd0;
83        if(csr_selected) begin
84            if(csr_we) begin
85                case(csr_a[3:0])
86                    4'd0: vga_rst <= csr_di[0];
87                    4'd1: hres <= csr_di[10:0];
88                    4'd2: hsync_start <= csr_di[10:0];
89                    4'd3: hsync_end <= csr_di[10:0];
90                    4'd4: hscan <= csr_di[10:0];
91                    4'd5: vres <= csr_di[10:0];
92                    4'd6: vsync_start <= csr_di[10:0];
93                    4'd7: vsync_end <= csr_di[10:0];
94                    4'd8: vscan <= csr_di[10:0];
95                    4'd9: baseaddress <= csr_di[fml_depth-1:0];
96                    // 10: baseaddress_act is read-only for Wishbone
97                    4'd11: nbursts <= csr_di[17:0];
98                    4'd12: vga_clk_sel <= csr_di[1:0];
99                endcase
100            end
101            
102            case(csr_a[3:0])
103                4'd0: csr_do <= vga_rst;
104                4'd1: csr_do <= hres;
105                4'd2: csr_do <= hsync_start;
106                4'd3: csr_do <= hsync_end;
107                4'd4: csr_do <= hscan;
108                4'd5: csr_do <= vres;
109                4'd6: csr_do <= vsync_start;
110                4'd7: csr_do <= vsync_end;
111                4'd8: csr_do <= vscan;
112                4'd9: csr_do <= baseaddress;
113                4'd10: csr_do <= baseaddress_act;
114                4'd11: csr_do <= nbursts;
115                4'd12: csr_do <= vga_clk_sel;
116            endcase
117        end
118    end
119end
120
121endmodule
122

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