Root/lm32/logic/sakc/cores/vgafb/rtl/vgafb_pixelfeed.v

1/*
2 * Milkymist VJ SoC
3 * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
4 *
5 * This program is free software: you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation, version 3 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18module vgafb_pixelfeed #(
19    parameter fml_depth = 26
20) (
21    input sys_clk,
22    /* We must take into account both resets :
23     * VGA reset should not interrupt a pending FML request
24     * but system reset should.
25     */
26    input sys_rst,
27    input vga_rst,
28    
29    input [17:0] nbursts,
30    input [fml_depth-1:0] baseaddress,
31    output baseaddress_ack,
32    
33    output reg [fml_depth-1:0] fml_adr,
34    output reg fml_stb,
35    input fml_ack,
36    input [63:0] fml_di,
37    
38    output pixel_valid,
39    output [15:0] pixel,
40    input pixel_ack
41);
42
43/* FIFO that stores the 64-bit bursts and slices it in 16-bit words */
44
45reg fifo_stb;
46wire fifo_valid;
47
48vgafb_fifo64to16 fifo64to16(
49    .sys_clk(sys_clk),
50    .vga_rst(vga_rst),
51    
52    .stb(fifo_stb),
53    .di(fml_di),
54    
55    .do_valid(fifo_valid),
56    .do(pixel),
57    .next(pixel_ack)
58);
59
60assign pixel_valid = fifo_valid;
61
62/* BURST COUNTER */
63reg sof;
64wire counter_en;
65
66reg [17:0] bcounter;
67
68always @(posedge sys_clk) begin
69    if(vga_rst) begin
70        bcounter <= 18'd1;
71        sof <= 1'b1;
72    end else begin
73        if(counter_en) begin
74            if(bcounter == nbursts) begin
75                bcounter <= 18'd1;
76                sof <= 1'b1;
77            end else begin
78                bcounter <= bcounter + 18'd1;
79                sof <= 1'b0;
80            end
81        end
82    end
83end
84
85/* FML ADDRESS GENERATOR */
86wire next_address;
87
88assign baseaddress_ack = sof & next_address;
89
90always @(posedge sys_clk) begin
91    if(sys_rst) begin
92        fml_adr <= {fml_depth{1'b0}};
93    end else begin
94        if(next_address) begin
95            if(sof)
96                fml_adr <= baseaddress;
97            else
98                fml_adr <= fml_adr + {{fml_depth-6{1'b0}}, 6'd32};
99        end
100    end
101end
102
103/* CONTROLLER */
104reg [2:0] state;
105reg [2:0] next_state;
106
107parameter IDLE = 3'd0;
108parameter WAIT = 3'd1;
109parameter FETCH2 = 3'd2;
110parameter FETCH3 = 3'd3;
111parameter FETCH4 = 3'd4;
112
113always @(posedge sys_clk) begin
114    if(sys_rst)
115        state <= IDLE;
116    else
117        state <= next_state;
118end
119
120/*
121 * Do not put spurious data into the FIFO if the VGA reset
122 * is asserted and released during the FML access. Getting
123 * the FIFO out of sync would result in distorted pictures
124 * we really want to avoid.
125 */
126
127reg ignore;
128reg ignore_clear;
129
130always @(posedge sys_clk) begin
131    if(vga_rst)
132        ignore <= 1'b1;
133    else if(ignore_clear)
134        ignore <= 1'b0;
135end
136
137reg next_burst;
138
139assign counter_en = next_burst;
140assign next_address = next_burst;
141
142always @(*) begin
143    next_state = state;
144    
145    fifo_stb = 1'b0;
146    next_burst = 1'b0;
147    
148    fml_stb = 1'b0;
149    ignore_clear = 1'b0;
150    
151    case(state)
152        IDLE: begin
153            if(~fifo_valid & ~vga_rst) begin
154                /* We're in need of pixels ! */
155                next_burst = 1'b1;
156                ignore_clear = 1'b1;
157                next_state = WAIT;
158            end
159        end
160        WAIT: begin
161            fml_stb = 1'b1;
162            if(fml_ack) begin
163                if(~ignore) fifo_stb = 1'b1;
164                next_state = FETCH2;
165             end
166        end
167        FETCH2: begin
168            if(~ignore) fifo_stb = 1'b1;
169            next_state = FETCH3;
170        end
171        FETCH3: begin
172            if(~ignore) fifo_stb = 1'b1;
173            next_state = FETCH4;
174        end
175        FETCH4: begin
176            if(~ignore) fifo_stb = 1'b1;
177            next_state = IDLE;
178        end
179    endcase
180end
181
182endmodule
183

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