Hardware Design: SIE
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| 1 | /* |
| 2 | * LatticeMico32 C startup code. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions |
| 6 | * are met: |
| 7 | * 1. Redistributions of source code must retain the above copyright |
| 8 | * notice, this list of conditions and the following disclaimer. |
| 9 | * 2. Redistributions in binary form must reproduce the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer in the |
| 11 | * documentation and/or other materials provided with the distribution. |
| 12 | * |
| 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND |
| 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE |
| 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 23 | * SUCH DAMAGE. |
| 24 | */ |
| 25 | |
| 26 | /* Exception handlers - Must be 32 bytes long. */ |
| 27 | .section .text, "ax", @progbits |
| 28 | .global _start |
| 29 | .global irq_enable, irq_disable, irq_mask, jump, halt |
| 30 | _start: |
| 31 | _reset_handler: |
| 32 | xor r0, r0, r0 |
| 33 | wcsr IE, r0 |
| 34 | mvhi r1, hi(_reset_handler) |
| 35 | ori r1, r1, lo(_reset_handler) |
| 36 | wcsr EBA, r1 |
| 37 | calli _crt0 |
| 38 | nop |
| 39 | nop |
| 40 | |
| 41 | _crt0: |
| 42 | /* Setup stack and global pointer */ |
| 43 | mvhi sp, hi(_fstack) |
| 44 | ori sp, sp, lo(_fstack) |
| 45 | mvhi gp, hi(_gp) |
| 46 | ori gp, gp, lo(_gp) |
| 47 | |
| 48 | /* Clear BSS */ |
| 49 | mvhi r1, hi(_fbss) |
| 50 | ori r1, r1, lo(_fbss) |
| 51 | mvhi r3, hi(_ebss) |
| 52 | ori r3, r3, lo(_ebss) |
| 53 | .clearBSS: |
| 54 | be r1, r3, .callMain |
| 55 | sw (r1+0), r0 |
| 56 | addi r1, r1, 4 |
| 57 | bi .clearBSS |
| 58 | |
| 59 | .callMain: |
| 60 | mvi r1, 0 |
| 61 | mvi r2, 0 |
| 62 | mvi r3, 0 |
| 63 | calli main |
| 64 | |
| 65 | irq_enable: |
| 66 | mvi r1, 1 |
| 67 | wcsr IE, r1 |
| 68 | ret |
| 69 | |
| 70 | irq_mask: |
| 71 | mvi r1, 0x0000000f |
| 72 | wcsr IM, r1 |
| 73 | ret |
| 74 | |
| 75 | irq_disable: |
| 76 | mvi r1, 0 |
| 77 | wcsr IE, r1 |
| 78 | ret |
| 79 | |
| 80 | jump: |
| 81 | b r1 |
| 82 | |
| 83 | halt: |
| 84 | bi halt |
| 85 | |
| 86 |
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