Hardware Design: SIE
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| 1 | #ifndef SPIKEHW_H |
| 2 | #define SPIKEHW_H |
| 3 | |
| 4 | #define PROMSTART 0x00000000 |
| 5 | #define RAMSTART 0x00000800 |
| 6 | #define RAMSIZE 0x400 |
| 7 | #define RAMEND (RAMSTART + RAMSIZE) |
| 8 | |
| 9 | #define RAM_START 0x40000000 |
| 10 | #define RAM_SIZE 0x04000000 |
| 11 | |
| 12 | #define FCPU 50000000 |
| 13 | |
| 14 | #define UART_RXBUFSIZE 32 |
| 15 | |
| 16 | /**************************************************************************** |
| 17 | * Types |
| 18 | */ |
| 19 | typedef unsigned int uint32_t; // 32 Bit |
| 20 | typedef signed int int32_t; // 32 Bit |
| 21 | |
| 22 | typedef unsigned char uint8_t; // 8 Bit |
| 23 | typedef signed char int8_t; // 8 Bit |
| 24 | |
| 25 | /**************************************************************************** |
| 26 | * Interrupt handling |
| 27 | */ |
| 28 | typedef void(*isr_ptr_t)(void); |
| 29 | |
| 30 | void irq_enable(); |
| 31 | void irq_disable(); |
| 32 | void irq_set_mask(uint32_t mask); |
| 33 | uint32_t irq_get_mak(); |
| 34 | |
| 35 | void isr_init(); |
| 36 | void isr_register(int irq, isr_ptr_t isr); |
| 37 | void isr_unregister(int irq); |
| 38 | |
| 39 | /**************************************************************************** |
| 40 | * General Stuff |
| 41 | */ |
| 42 | void halt(); |
| 43 | void jump(uint32_t addr); |
| 44 | |
| 45 | |
| 46 | /**************************************************************************** |
| 47 | * Timer |
| 48 | */ |
| 49 | #define TIMER_EN 0x08 // Enable Timer |
| 50 | #define TIMER_AR 0x04 // Auto-Reload |
| 51 | #define TIMER_IRQEN 0x02 // IRQ Enable |
| 52 | #define TIMER_TRIG 0x01 // Triggered (reset when writing to TCR) |
| 53 | |
| 54 | typedef struct { |
| 55 | volatile uint32_t tcr0; |
| 56 | volatile uint32_t compare0; |
| 57 | volatile uint32_t counter0; |
| 58 | volatile uint32_t tcr1; |
| 59 | volatile uint32_t compare1; |
| 60 | volatile uint32_t counter1; |
| 61 | } timer_t; |
| 62 | |
| 63 | void msleep(uint32_t msec); |
| 64 | void nsleep(uint32_t nsec); |
| 65 | |
| 66 | void tic_init(); |
| 67 | |
| 68 | |
| 69 | /*************************************************************************** |
| 70 | * GPIO0 |
| 71 | */ |
| 72 | typedef struct { |
| 73 | volatile uint32_t ctrl; |
| 74 | volatile uint32_t dummy1; |
| 75 | volatile uint32_t dummy2; |
| 76 | volatile uint32_t dummy3; |
| 77 | volatile uint32_t in; |
| 78 | volatile uint32_t out; |
| 79 | volatile uint32_t oe; |
| 80 | } gpio_t; |
| 81 | |
| 82 | /*************************************************************************** |
| 83 | * UART0 |
| 84 | */ |
| 85 | #define UART_DR 0x01 // RX Data Ready |
| 86 | #define UART_ERR 0x02 // RX Error |
| 87 | #define UART_BUSY 0x10 // TX Busy |
| 88 | |
| 89 | typedef struct { |
| 90 | volatile uint32_t ucr; |
| 91 | volatile uint32_t rxtx; |
| 92 | } uart_t; |
| 93 | |
| 94 | void uart_init(); |
| 95 | void uart_putchar(char c); |
| 96 | void uart_putstr(char *str); |
| 97 | char uart_getchar(); |
| 98 | |
| 99 | |
| 100 | /*************************************************************************** |
| 101 | * Pointer to actual components |
| 102 | */ |
| 103 | extern timer_t *timer0; |
| 104 | extern uart_t *uart0; |
| 105 | extern gpio_t *gpio0; |
| 106 | extern uint32_t *sram0; |
| 107 | |
| 108 | #endif // SPIKEHW_H |
| 109 |
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