Root/lm32/logic/sakc/firmware/ddr-phaser/crt0ram.S

1/*
2 * LatticeMico32 C startup code.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26/* Exception handlers - Must be 32 bytes long. */
27        .section .text, "ax", @progbits
28        .global _start
29        .global irq_enable, irq_disable, irq_mask, jump, halt
30_start:
31_reset_handler:
32    xor r0, r0, r0
33    wcsr IE, r0
34    mvhi r1, hi(_reset_handler)
35    ori r1, r1, lo(_reset_handler)
36    wcsr EBA, r1
37    calli _crt0
38    nop
39    nop
40
41_crt0:
42    /* Setup stack and global pointer */
43    mvhi sp, hi(_fstack)
44    ori sp, sp, lo(_fstack)
45    mvhi gp, hi(_gp)
46    ori gp, gp, lo(_gp)
47
48    /* Clear BSS */
49    mvhi r1, hi(_fbss)
50    ori r1, r1, lo(_fbss)
51    mvhi r3, hi(_ebss)
52    ori r3, r3, lo(_ebss)
53.clearBSS:
54    be r1, r3, .callMain
55    sw (r1+0), r0
56    addi r1, r1, 4
57    bi .clearBSS
58    
59.callMain:
60    mvi r1, 0
61    mvi r2, 0
62    mvi r3, 0
63    calli main
64
65irq_enable:
66    mvi r1, 1
67    wcsr IE, r1
68    ret
69
70irq_mask:
71    mvi r1, 0x0000000f
72    wcsr IM, r1
73    ret
74    
75irq_disable:
76    mvi r1, 0
77    wcsr IE, r1
78    ret
79
80jump:
81    b r1
82
83halt:
84    bi halt
85
86    /* Save all registers onto the stack */
87_save_all:
88    addi sp, sp, -128
89    sw (sp+4), r1
90    sw (sp+8), r2
91    sw (sp+12), r3
92    sw (sp+16), r4
93    sw (sp+20), r5
94    sw (sp+24), r6
95    sw (sp+28), r7
96    sw (sp+32), r8
97    sw (sp+36), r9
98    sw (sp+40), r10
99#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
100    sw (sp+44), r11
101    sw (sp+48), r12
102    sw (sp+52), r13
103    sw (sp+56), r14
104    sw (sp+60), r15
105    sw (sp+64), r16
106    sw (sp+68), r17
107    sw (sp+72), r18
108    sw (sp+76), r19
109    sw (sp+80), r20
110    sw (sp+84), r21
111    sw (sp+88), r22
112    sw (sp+92), r23
113    sw (sp+96), r24
114    sw (sp+100), r25
115    sw (sp+104), r26
116    sw (sp+108), r27
117#endif
118    sw (sp+120), ea
119    sw (sp+124), ba
120    /* ra and sp need special handling, as they have been modified */
121    lw r1, (sp+128)
122    sw (sp+116), r1
123    mv r1, sp
124    addi r1, r1, 128
125    sw (sp+112), r1
126    ret
127
128        /* Restore all registers and return from exception */
129_restore_all_and_return:
130        lw r1, (sp+4)
131        lw r2, (sp+8)
132        lw r3, (sp+12)
133        lw r4, (sp+16)
134        lw r5, (sp+20)
135        lw r6, (sp+24)
136        lw r7, (sp+28)
137        lw r8, (sp+32)
138        lw r9, (sp+36)
139        lw r10, (sp+40)
140#ifdef MICO32_FULL_CONTEXT_SAVE_RESTORE
141        lw r11, (sp+44)
142        lw r12, (sp+48)
143        lw r13, (sp+52)
144        lw r14, (sp+56)
145        lw r15, (sp+60)
146        lw r16, (sp+64)
147        lw r17, (sp+68)
148        lw r18, (sp+72)
149        lw r19, (sp+76)
150        lw r20, (sp+80)
151        lw r21, (sp+84)
152        lw r22, (sp+88)
153        lw r23, (sp+92)
154        lw r24, (sp+96)
155        lw r25, (sp+100)
156        lw r26, (sp+104)
157        lw r27, (sp+108)
158#endif
159        lw ra, (sp+116)
160        lw ea, (sp+120)
161        lw ba, (sp+124)
162        /* Stack pointer must be restored last, in case it has been updated */
163        lw sp, (sp+112)
164        eret
165
166
167

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