Root/lm32/logic/sakc/rtl/lm32/JTAGB.v

1module JTAGB (
2         output JTCK,
3         output JRTI1,
4         output JRTI2,
5         output JTDI,
6         output JSHIFT,
7         output JUPDATE,
8         output JRSTN,
9         output JCE1,
10         output JCE2,
11         input JTDO1,
12         input JTDO2
13      ) /*synthesis syn_black_box */;
14      
15endmodule
16

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