Root/lm32/logic/sakc/rtl/lm32/er1.v

1/*-- ---------------------------------------------------------------------------
2--
3-- Name : ER1.v
4--
5-- Description:
6--
7-- This module is where the ER1 register implemented. ER1 and ER2 registers
8-- can be registers implemented in Lattice FPGAs using normal FPGA's
9-- programmable logic resources. Once they are implemented, they can be
10-- accessed as if they are JTAG data registers through the FPGA JTAG port.
11-- In order to accessing these registers, JTAG instructions ER1(0x32) or
12-- ER2(0x38) needs to be written to the JTAG IR register for enabling the
13-- ER1/ER2 accessing logic. The ER1 or ER2 accessing logic can only be
14-- enabled one at a time. Once they are enabled, they will be disabled if
15-- another JTAG instruction is written into the JTAG instruction register.
16-- The registers allow dynamically accessing the FPGA internal information
17-- even when the device is running. Therefore, they are very useful for some
18-- of the IP cores. In order to let ER1/ER2 registers shared by multiple IP
19-- cores or other designs, there is a ER1/ER2 structure patterned by Lattice.
20-- The ER1/ER2 structure allows only one ER1 register but more than one ER2
21-- registers in an FPGA device. Please refer to the related document for
22-- this patterned ER1/ER2 structure.
23--
24-- $Log: $
25--
26-- $Header: $
27--
28-- Copyright (C) 2004 Lattice Semiconductor Corp. All rights reserved.
29--
30-- ---------------------------------------------------------------------------*/
31
32module ER1 (input JTCK,
33        input JTDI,
34        output JTDO1,
35        output reg JTDO2,
36        input JSHIFT,
37        input JUPDATE,
38        input JRSTN,
39        input JCE1,
40        input [14:0] ER2_TDO,
41        output reg [14:0] IP_ENABLE,
42        input ISPTRACY_ER2_TDO,
43        output ISPTRACY_ENABLE,
44        output CONTROL_DATAN)/* synthesis syn_hier = hard */;
45
46
47   wire controlDataNBit;
48   wire ispTracyEnableBit;
49   wire [3:0] encodedIpEnableBits;
50   wire [9:0] er1TdiBit;
51   wire captureDrER1;
52   
53
54   assign JTDO1 = er1TdiBit[0];
55   
56   TYPEB BIT0 (.CLK(JTCK),
57           .RESET_N(JRSTN),
58           .CLKEN(JCE1),
59           .TDI(er1TdiBit[1]),
60           .TDO(er1TdiBit[0]),
61           .DATA_IN(1'b0),
62           .CAPTURE_DR(captureDrER1));
63
64   TYPEB BIT1 (.CLK(JTCK),
65           .RESET_N(JRSTN),
66           .CLKEN(JCE1),
67           .TDI(er1TdiBit[2]),
68           .TDO(er1TdiBit[1]),
69           .DATA_IN(1'b0),
70           .CAPTURE_DR(captureDrER1));
71
72   TYPEB BIT2 (.CLK(JTCK),
73           .RESET_N(JRSTN),
74           .CLKEN(JCE1),
75           .TDI(er1TdiBit[3]),
76           .TDO(er1TdiBit[2]),
77           .DATA_IN(1'b1),
78           .CAPTURE_DR(captureDrER1));
79   
80   TYPEA BIT3 (.CLK(JTCK),
81           .RESET_N(JRSTN),
82           .CLKEN(JCE1),
83           .TDI(er1TdiBit[4]),
84           .TDO(er1TdiBit[3]),
85           .DATA_OUT(controlDataNBit),
86           .DATA_IN(controlDataNBit),
87           .CAPTURE_DR(captureDrER1),
88           .UPDATE_DR(JUPDATE));
89
90   assign CONTROL_DATAN = controlDataNBit;
91
92   TYPEA BIT4 (.CLK(JTCK),
93           .RESET_N(JRSTN),
94           .CLKEN(JCE1),
95           .TDI(er1TdiBit[5]),
96           .TDO(er1TdiBit[4]),
97           .DATA_OUT(ispTracyEnableBit),
98           .DATA_IN(ispTracyEnableBit),
99           .CAPTURE_DR(captureDrER1),
100           .UPDATE_DR(JUPDATE)
101           );
102
103   assign ISPTRACY_ENABLE = ispTracyEnableBit;
104
105   TYPEA BIT5 (.CLK(JTCK),
106           .RESET_N(JRSTN),
107           .CLKEN(JCE1),
108           .TDI(er1TdiBit[6]),
109           .TDO(er1TdiBit[5]),
110           .DATA_OUT(encodedIpEnableBits[0]),
111           .DATA_IN(encodedIpEnableBits[0]),
112           .CAPTURE_DR(captureDrER1),
113           .UPDATE_DR(JUPDATE));
114   
115   TYPEA BIT6 (.CLK(JTCK),
116           .RESET_N(JRSTN),
117           .CLKEN(JCE1),
118           .TDI(er1TdiBit[7]),
119           .TDO(er1TdiBit[6]),
120           .DATA_OUT(encodedIpEnableBits[1]),
121           .DATA_IN(encodedIpEnableBits[1]),
122           .CAPTURE_DR(captureDrER1),
123           .UPDATE_DR(JUPDATE));
124   
125   TYPEA BIT7 (.CLK(JTCK),
126           .RESET_N(JRSTN),
127           .CLKEN(JCE1),
128           .TDI(er1TdiBit[8]),
129           .TDO(er1TdiBit[7]),
130           .DATA_OUT(encodedIpEnableBits[2]),
131           .DATA_IN(encodedIpEnableBits[2]),
132           .CAPTURE_DR(captureDrER1),
133           .UPDATE_DR(JUPDATE));
134   
135   TYPEA BIT8 (.CLK(JTCK),
136           .RESET_N(JRSTN),
137           .CLKEN(JCE1),
138           .TDI(er1TdiBit[9]),
139           .TDO(er1TdiBit[8]),
140           .DATA_OUT(encodedIpEnableBits[3]),
141           .DATA_IN(encodedIpEnableBits[3]),
142           .CAPTURE_DR(captureDrER1),
143           .UPDATE_DR(JUPDATE)
144           );
145   
146   assign er1TdiBit[9] = JTDI;
147   assign captureDrER1 = !JSHIFT & JCE1;
148   
149   always @ (encodedIpEnableBits,ISPTRACY_ER2_TDO, ER2_TDO)
150   begin
151    case (encodedIpEnableBits)
152      4'h0: begin
153              IP_ENABLE <= 15'b000000000000000;
154              JTDO2 <= ISPTRACY_ER2_TDO;
155              end
156      4'h1: begin
157              IP_ENABLE <= 15'b000000000000001;
158              JTDO2 <= ER2_TDO[0];
159              end
160      4'h2: begin
161              IP_ENABLE <= 15'b000000000000010;
162              JTDO2 <= ER2_TDO[1];
163              end
164      4'h3: begin
165              IP_ENABLE <= 15'b000000000000100;
166              JTDO2 <= ER2_TDO[2];
167              end
168      4'h4: begin
169              IP_ENABLE <= 15'b000000000001000;
170              JTDO2 <= ER2_TDO[3];
171              end
172      4'h5: begin
173              IP_ENABLE <= 15'b000000000010000;
174              JTDO2 <= ER2_TDO[4];
175              end
176      4'h6: begin
177              IP_ENABLE <= 15'b000000000100000;
178              JTDO2 <= ER2_TDO[5];
179              end
180      4'h7: begin
181              IP_ENABLE <= 15'b000000001000000;
182              JTDO2 <= ER2_TDO[6];
183              end
184      4'h8: begin
185              IP_ENABLE <= 15'b000000010000000;
186              JTDO2 <= ER2_TDO[7];
187              end
188      4'h9: begin
189              IP_ENABLE <= 15'b000000100000000;
190              JTDO2 <= ER2_TDO[8];
191              end
192      4'hA: begin
193              IP_ENABLE <= 15'b000001000000000;
194              JTDO2 <= ER2_TDO[9];
195              end
196      4'hB: begin
197              IP_ENABLE <= 15'b000010000000000;
198              JTDO2 <= ER2_TDO[10];
199              end
200      4'hC: begin
201              IP_ENABLE <= 15'b000100000000000;
202              JTDO2 <= ER2_TDO[11];
203              end
204      4'hD: begin
205              IP_ENABLE <= 15'b001000000000000;
206              JTDO2 <= ER2_TDO[12];
207              end
208      4'hE: begin
209              IP_ENABLE <= 15'b010000000000000;
210              JTDO2 <= ER2_TDO[13];
211              end
212      4'hF: begin
213              IP_ENABLE <= 15'b100000000000000;
214              JTDO2 <= ER2_TDO[14];
215              end
216    endcase
217  end
218endmodule
219

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