Root/lm32/logic/sakc/rtl/lm32/jtag_cores.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : jtag_cores.v
19// Title : Instantiates all IP cores on JTAG chain.
20// Dependencies : system_conf.v
21// Version : 6.0.13
22// =============================================================================
23
24`include "system_conf.v"
25
26/////////////////////////////////////////////////////
27// Module interface
28/////////////////////////////////////////////////////
29
30module jtag_cores (
31    // ----- Inputs -------
32`ifdef INCLUDE_LM32
33    reg_d,
34    reg_addr_d,
35`endif
36`ifdef INCLUDE_SPI
37    spi_q,
38`endif
39    // ----- Outputs -------
40`ifdef INCLUDE_LM32
41    reg_update,
42    reg_q,
43    reg_addr_q,
44`endif
45`ifdef INCLUDE_SPI
46    spi_c,
47    spi_d,
48    spi_sn,
49`endif
50    jtck,
51    jrstn
52    );
53    
54/////////////////////////////////////////////////////
55// Inputs
56/////////////////////////////////////////////////////
57
58`ifdef INCLUDE_LM32
59input [7:0] reg_d;
60input [2:0] reg_addr_d;
61`endif
62
63`ifdef INCLUDE_SPI
64input spi_q;
65`endif
66
67/////////////////////////////////////////////////////
68// Outputs
69/////////////////////////////////////////////////////
70   
71`ifdef INCLUDE_LM32
72output reg_update;
73wire reg_update;
74output [7:0] reg_q;
75wire [7:0] reg_q;
76output [2:0] reg_addr_q;
77wire [2:0] reg_addr_q;
78`endif
79
80`ifdef INCLUDE_SPI
81output spi_c;
82wire spi_c;
83output spi_d;
84wire spi_d;
85output spi_sn;
86wire spi_sn;
87`endif
88
89output jtck;
90wire jtck; /* synthesis ER1_MARK="jtck" */ /* synthesis syn_keep=1 */
91output jrstn;
92wire jrstn; /* synthesis ER1_MARK="jrstn" */ /* synthesis syn_keep=1 */
93
94   
95/////////////////////////////////////////////////////
96// Internal nets and registers
97/////////////////////////////////////////////////////
98
99wire rtiER1;
100wire rtiER2;
101wire tdi;/* synthesis ER1_MARK="jtdi" */ /* synthesis syn_keep=1 */
102wire tdoEr1;/* synthesis ER1_MARK="jtdo1" */ /* synthesis syn_keep=1 */
103wire tdoEr2;
104wire jtdo2_mux;/* synthesis ER1_MARK="jtdo2" */ /* synthesis syn_keep=1 */
105wire spi_tdo2;
106wire shiftDr;/* synthesis ER1_MARK="jshift" */ /* synthesis syn_keep=1 */
107wire updateDr;/* synthesis ER1_MARK="jupdate" */ /* synthesis syn_keep=1 */
108wire enableEr1;/* synthesis ER1_MARK="jce1" */ /* synthesis syn_keep=1 */
109wire enableEr2;/* synthesis ER1_MARK="jce2" */ /* synthesis syn_keep=1 */
110wire [14:0] ipEnable;/* synthesis ER1_MARK="ip_enable" */ /* synthesis syn_keep=1 */
111wire controlDataN;/* synthesis ER1_MARK="control_datan" */ /* synthesis syn_keep=1 */
112wire lm32_isptracy_enable;/* synthesis ER1_MARK="isptracy_enable" */ /* synthesis syn_keep=1 */
113
114
115/////////////////////////////////////////////////////
116// Instantiations
117/////////////////////////////////////////////////////
118     parameter lat_family = `LATTICE_FAMILY;
119   
120generate
121   if (lat_family == "EC" || lat_family == "ECP" || lat_family == "XP") begin
122     JTAGB jtagb (.JTCK (jtck),
123          .JRTI1 (rtiER1),
124          .JRTI2 (rtiER2),
125          .JTDI (tdi),
126          .JSHIFT (shiftDr),
127          .JUPDATE (updateDr),
128          .JRSTN (jrstn),
129          .JCE1 (enableEr1),
130          .JCE2 (enableEr2),
131          .JTDO1 (tdoEr1),
132          .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
133   end else if (lat_family == "ECP2" || lat_family == "ECP2M") begin
134     JTAGC jtagc (.JTCK (jtck),
135          .JRTI1 (rtiER1),
136          .JRTI2 (rtiER2),
137          .JTDI (tdi),
138          .JSHIFT (shiftDr),
139          .JUPDATE (updateDr),
140          .JRSTN (jrstn),
141          .IJTAGEN (1'b1),
142          .JCE1 (enableEr1),
143          .JCE2 (enableEr2),
144          .JTDO1 (tdoEr1),
145          .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
146   end else if (lat_family == "SC" || lat_family == "SCM") begin // if (lat_family == "ECP2" || lat_family == "ECP2M")
147      JTAGA jtaga(.JTCK (jtck),
148          .JRTI1 (rtiER1),
149          .JRTI2 (rtiER2),
150          .JTDI (tdi),
151          .JSHIFT (shiftDr),
152          .JUPDATE (updateDr),
153          .JRSTN (jrstn),
154          .JCE1 (enableEr1),
155          .JCE2 (enableEr2),
156          .JTDO1 (tdoEr1),
157          .JTDO2 (jtdo2_mux)) /* synthesis ER1="ENABLED" */ /* synthesis ER2="ENABLED" */ /* synthesis JTAG_FLASH_PRGRM="DISABLED" */;
158   end
159endgenerate
160
161ER1 er1 (
162    .JTCK (jtck),
163    .JTDI (tdi),
164    .JTDO1 (tdoEr1),
165    .JTDO2 (jtdo2_mux),
166    .JSHIFT (shiftDr),
167    .JUPDATE (updateDr),
168    .JRSTN (jrstn),
169    .JCE1 (enableEr1),
170    .ER2_TDO ({13'b0,tdoEr2,spi_tdo2}),
171    .IP_ENABLE (ipEnable),
172    .ISPTRACY_ENABLE(lm32_isptracy_enable),
173    .ISPTRACY_ER2_TDO(lm32_isptracy_enable),
174    .CONTROL_DATAN (controlDataN));
175
176`ifdef INCLUDE_LM32
177jtag_lm32 jtag_lm32 (
178    .JTCK (jtck),
179    .JTDI (tdi),
180    .JTDO2 (tdoEr2),
181    .JSHIFT (shiftDr),
182    .JUPDATE (updateDr),
183    .JRSTN (jrstn),
184    .JCE2 (enableEr2),
185    .JTAGREG_ENABLE (ipEnable[1]),
186    .CONTROL_DATAN (controlDataN),
187    .REG_UPDATE (reg_update),
188    .REG_D (reg_d),
189    .REG_ADDR_D (reg_addr_d),
190    .REG_Q (reg_q),
191    .REG_ADDR_Q (reg_addr_q)
192    );
193`endif
194
195`ifdef INCLUDE_SPI
196SPIPROG spiprog_inst (
197     .JTCK (tck),
198     .JTDI (tdi),
199     .JTDO2 (spi_tdo2),
200     .JSHIFT (shiftDr),
201     .JUPDATE (updateDr),
202     .JRSTN (resetN),
203     .JCE2 (enableEr2),
204     .SPIPROG_ENABLE (ipEnable[0]),
205     .CONTROL_DATAN (controlDataN),
206     .SPI_C (spi_c),
207     .SPI_D (spi_d),
208     .SPI_SN (spi_sn),
209     .SPI_Q (spi_q)
210     );
211`endif
212    
213endmodule
214

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