Root/lm32/logic/sakc/rtl/lm32/jtag_lm32.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : jtag_lm32.v
19// Title : JTAG data register for LM32 CPU debug interface
20// Version : 6.0.13
21// =============================================================================
22
23/////////////////////////////////////////////////////
24// Module interface
25/////////////////////////////////////////////////////
26
27module jtag_lm32 (
28    input JTCK,
29    input JTDI,
30    output JTDO2,
31    input JSHIFT,
32    input JUPDATE,
33    input JRSTN,
34    input JCE2,
35    input JTAGREG_ENABLE,
36    input CONTROL_DATAN,
37    output REG_UPDATE,
38    input [7:0] REG_D,
39    input [2:0] REG_ADDR_D,
40    output [7:0] REG_Q,
41    output [2:0] REG_ADDR_Q
42    );
43
44/////////////////////////////////////////////////////
45// Internal nets and registers
46/////////////////////////////////////////////////////
47
48wire [9:0] tdibus;
49
50/////////////////////////////////////////////////////
51// Instantiations
52/////////////////////////////////////////////////////
53   
54TYPEA DATA_BIT0 (
55    .CLK(JTCK),
56    .RESET_N(JRSTN),
57    .CLKEN(clk_enable),
58    .TDI(JTDI),
59    .TDO(tdibus[0]),
60    .DATA_OUT(REG_Q[0]),
61    .DATA_IN(REG_D[0]),
62    .CAPTURE_DR(captureDr),
63    .UPDATE_DR(JUPDATE)
64    );
65
66TYPEA DATA_BIT1 (
67    .CLK(JTCK),
68    .RESET_N(JRSTN),
69    .CLKEN(clk_enable),
70    .TDI(tdibus[0]),
71    .TDO(tdibus[1]),
72    .DATA_OUT(REG_Q[1]),
73    .DATA_IN(REG_D[1]),
74    .CAPTURE_DR(captureDr),
75    .UPDATE_DR(JUPDATE)
76    );
77
78TYPEA DATA_BIT2 (
79    .CLK(JTCK),
80    .RESET_N(JRSTN),
81    .CLKEN(clk_enable),
82    .TDI(tdibus[1]),
83    .TDO(tdibus[2]),
84    .DATA_OUT(REG_Q[2]),
85    .DATA_IN(REG_D[2]),
86    .CAPTURE_DR(captureDr),
87    .UPDATE_DR(JUPDATE)
88    );
89
90TYPEA DATA_BIT3 (
91    .CLK(JTCK),
92    .RESET_N(JRSTN),
93    .CLKEN(clk_enable),
94    .TDI(tdibus[2]),
95    .TDO(tdibus[3]),
96    .DATA_OUT(REG_Q[3]),
97    .DATA_IN(REG_D[3]),
98    .CAPTURE_DR(captureDr),
99    .UPDATE_DR(JUPDATE)
100    );
101
102TYPEA DATA_BIT4 (
103    .CLK(JTCK),
104    .RESET_N(JRSTN),
105    .CLKEN(clk_enable),
106    .TDI(tdibus[3]),
107    .TDO(tdibus[4]),
108    .DATA_OUT(REG_Q[4]),
109    .DATA_IN(REG_D[4]),
110    .CAPTURE_DR(captureDr),
111    .UPDATE_DR(JUPDATE)
112    );
113
114TYPEA DATA_BIT5 (
115    .CLK(JTCK),
116    .RESET_N(JRSTN),
117    .CLKEN(clk_enable),
118    .TDI(tdibus[4]),
119    .TDO(tdibus[5]),
120    .DATA_OUT(REG_Q[5]),
121    .DATA_IN(REG_D[5]),
122    .CAPTURE_DR(captureDr),
123    .UPDATE_DR(JUPDATE)
124    );
125
126TYPEA DATA_BIT6 (
127    .CLK(JTCK),
128    .RESET_N(JRSTN),
129    .CLKEN(clk_enable),
130    .TDI(tdibus[5]),
131    .TDO(tdibus[6]),
132    .DATA_OUT(REG_Q[6]),
133    .DATA_IN(REG_D[6]),
134    .CAPTURE_DR(captureDr),
135    .UPDATE_DR(JUPDATE)
136    );
137
138TYPEA DATA_BIT7 (
139    .CLK(JTCK),
140    .RESET_N(JRSTN),
141    .CLKEN(clk_enable),
142    .TDI(tdibus[6]),
143    .TDO(tdibus[7]),
144    .DATA_OUT(REG_Q[7]),
145    .DATA_IN(REG_D[7]),
146    .CAPTURE_DR(captureDr),
147    .UPDATE_DR(JUPDATE)
148    );
149
150TYPEA ADDR_BIT0 (
151    .CLK(JTCK),
152    .RESET_N(JRSTN),
153    .CLKEN(clk_enable),
154    .TDI(tdibus[7]),
155    .TDO(tdibus[8]),
156    .DATA_OUT(REG_ADDR_Q[0]),
157    .DATA_IN(REG_ADDR_D[0]),
158    .CAPTURE_DR(captureDr),
159    .UPDATE_DR(JUPDATE)
160    );
161
162TYPEA ADDR_BIT1 (
163    .CLK(JTCK),
164    .RESET_N(JRSTN),
165    .CLKEN(clk_enable),
166    .TDI(tdibus[8]),
167    .TDO(tdibus[9]),
168    .DATA_OUT(REG_ADDR_Q[1]),
169    .DATA_IN(REG_ADDR_D[1]),
170    .CAPTURE_DR(captureDr),
171    .UPDATE_DR(JUPDATE)
172    );
173
174TYPEA ADDR_BIT2 (
175    .CLK(JTCK),
176    .RESET_N(JRSTN),
177    .CLKEN(clk_enable),
178    .TDI(tdibus[9]),
179    .TDO(JTDO2),
180    .DATA_OUT(REG_ADDR_Q[2]),
181    .DATA_IN(REG_ADDR_D[2]),
182    .CAPTURE_DR(captureDr),
183    .UPDATE_DR(JUPDATE)
184    );
185
186/////////////////////////////////////////////////////
187// Combinational logic
188/////////////////////////////////////////////////////
189
190assign clk_enable = JTAGREG_ENABLE & JCE2;
191assign captureDr = !JSHIFT & JCE2;
192// JCE2 is only active during shift
193assign REG_UPDATE = JTAGREG_ENABLE & JUPDATE;
194 
195endmodule
196

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