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Root/lm32/logic/sakc/rtl/lm32/lm32_cpu.v

1	// =============================================================================
2	// COPYRIGHT NOTICE
3	// Copyright 2006 (c) Lattice Semiconductor Corporation
4	// ALL RIGHTS RESERVED
5	// This confidential and proprietary software may be used only as authorised by
6	// a licensing agreement from Lattice Semiconductor Corporation.
7	// The entire notice above must be reproduced on all authorized copies and
8	// copies may only be made to the extent permitted by a licensing agreement from
9	// Lattice Semiconductor Corporation.
10	//
11	// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12	// 5555 NE Moore Court 408-826-6000 (other locations)
13	// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14	// U.S.A email: techsupport@latticesemi.com
15	// =============================================================================/
16	// FILE DETAILS
17	// Project : LatticeMico32
18	// File : lm32_cpu.v
19	// Title : Top-level of CPU.
20	// Dependencies : lm32_include.v
21	// Version : 6.1.17
22	// =============================================================================
23
24	`include "lm32_include.v"
25
26	/////////////////////////////////////////////////////
27	// Module interface
28	/////////////////////////////////////////////////////
29
30	module lm32_cpu (
31	// ----- Inputs -------
32	clk_i,
33	`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
34	clk_n_i,
35	`endif
36	rst_i,
37	// From external devices
38	`ifdef CFG_INTERRUPTS_ENABLED
39	interrupt_n,
40	`endif
41	// From user logic
42	`ifdef CFG_USER_ENABLED
43	user_result,
44	user_complete,
45	`endif
46	`ifdef CFG_JTAG_ENABLED
47	// From JTAG
48	jtag_clk,
49	jtag_update,
50	jtag_reg_q,
51	jtag_reg_addr_q,
52	`endif
53	`ifdef CFG_IWB_ENABLED
54	// Instruction Wishbone master
55	I_DAT_I,
56	I_ACK_I,
57	I_ERR_I,
58	I_RTY_I,
59	`endif
60	// Data Wishbone master
61	D_DAT_I,
62	D_ACK_I,
63	D_ERR_I,
64	D_RTY_I,
65	// ----- Outputs -------
66	`ifdef CFG_TRACE_ENABLED
67	trace_pc,
68	trace_pc_valid,
69	trace_exception,
70	trace_eid,
71	trace_eret,
72	`ifdef CFG_DEBUG_ENABLED
73	trace_bret,
74	`endif
75	`endif
76	`ifdef CFG_JTAG_ENABLED
77	jtag_reg_d,
78	jtag_reg_addr_d,
79	`endif
80	`ifdef CFG_USER_ENABLED
81	user_valid,
82	user_opcode,
83	user_operand_0,
84	user_operand_1,
85	`endif
86	`ifdef CFG_IWB_ENABLED
87	// Instruction Wishbone master
88	I_DAT_O,
89	I_ADR_O,
90	I_CYC_O,
91	I_SEL_O,
92	I_STB_O,
93	I_WE_O,
94	I_CTI_O,
95	I_LOCK_O,
96	I_BTE_O,
97	`endif
98	// Data Wishbone master
99	D_DAT_O,
100	D_ADR_O,
101	D_CYC_O,
102	D_SEL_O,
103	D_STB_O,
104	D_WE_O,
105	D_CTI_O,
106	D_LOCK_O,
107	D_BTE_O
108	);
109
110	/////////////////////////////////////////////////////
111	// Parameters
112	/////////////////////////////////////////////////////
113
114	parameter eba_reset = `CFG_EBA_RESET; // Reset value for EBA CSR
115	`ifdef CFG_DEBUG_ENABLED
116	parameter deba_reset = `CFG_DEBA_RESET; // Reset value for DEBA CSR
117	`endif
118
119	`ifdef CFG_ICACHE_ENABLED
120	parameter icache_associativity = `CFG_ICACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
121	parameter icache_sets = `CFG_ICACHE_SETS; // Number of sets
122	parameter icache_bytes_per_line = `CFG_ICACHE_BYTES_PER_LINE; // Number of bytes per cache line
123	parameter icache_base_address = `CFG_ICACHE_BASE_ADDRESS; // Base address of cachable memory
124	parameter icache_limit = `CFG_ICACHE_LIMIT; // Limit (highest address) of cachable memory
125	`else
126	parameter icache_associativity = 1;
127	parameter icache_sets = 512;
128	parameter icache_bytes_per_line = 16;
129	parameter icache_base_address = 0;
130	parameter icache_limit = 0;
131	`endif
132
133	`ifdef CFG_DCACHE_ENABLED
134	parameter dcache_associativity = `CFG_DCACHE_ASSOCIATIVITY; // Associativity of the cache (Number of ways)
135	parameter dcache_sets = `CFG_DCACHE_SETS; // Number of sets
136	parameter dcache_bytes_per_line = `CFG_DCACHE_BYTES_PER_LINE; // Number of bytes per cache line
137	parameter dcache_base_address = `CFG_DCACHE_BASE_ADDRESS; // Base address of cachable memory
138	parameter dcache_limit = `CFG_DCACHE_LIMIT; // Limit (highest address) of cachable memory
139	`else
140	parameter dcache_associativity = 1;
141	parameter dcache_sets = 512;
142	parameter dcache_bytes_per_line = 16;
143	parameter dcache_base_address = 0;
144	parameter dcache_limit = 0;
145	`endif
146
147	`ifdef CFG_DEBUG_ENABLED
148	parameter watchpoints = `CFG_WATCHPOINTS; // Number of h/w watchpoint CSRs
149	`else
150	parameter watchpoints = 4'h0;
151	`endif
152	`ifdef CFG_ROM_DEBUG_ENABLED
153	parameter breakpoints = `CFG_BREAKPOINTS; // Number of h/w breakpoint CSRs
154	`else
155	parameter breakpoints = 4'h0;
156	`endif
157
158	`ifdef CFG_INTERRUPTS_ENABLED
159	parameter interrupts = `CFG_INTERRUPTS; // Number of interrupts
160	`else
161	parameter interrupts = 0;
162	`endif
163
164	/////////////////////////////////////////////////////
165	// Inputs
166	/////////////////////////////////////////////////////
167
168	input clk_i; // Clock
169	`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
170	input clk_n_i; // Inverted clock
171	`endif
172	input rst_i; // Reset
173
174	`ifdef CFG_INTERRUPTS_ENABLED
175	input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
176	`endif
177
178	`ifdef CFG_USER_ENABLED
179	input [`LM32_WORD_RNG] user_result; // User-defined instruction result
180	input user_complete; // User-defined instruction execution is complete
181	`endif
182
183	`ifdef CFG_JTAG_ENABLED
184	input jtag_clk; // JTAG clock
185	input jtag_update; // JTAG state machine is in data register update state
186	input [`LM32_BYTE_RNG] jtag_reg_q;
187	input [2:0] jtag_reg_addr_q;
188	`endif
189
190	`ifdef CFG_IWB_ENABLED
191	input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
192	input I_ACK_I; // Instruction Wishbone interface acknowledgement
193	input I_ERR_I; // Instruction Wishbone interface error
194	input I_RTY_I; // Instruction Wishbone interface retry
195	`endif
196
197	input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
198	input D_ACK_I; // Data Wishbone interface acknowledgement
199	input D_ERR_I; // Data Wishbone interface error
200	input D_RTY_I; // Data Wishbone interface retry
201
202	/////////////////////////////////////////////////////
203	// Outputs
204	/////////////////////////////////////////////////////
205
206	`ifdef CFG_TRACE_ENABLED
207	output [`LM32_PC_RNG] trace_pc; // PC to trace
208	reg [`LM32_PC_RNG] trace_pc;
209	output trace_pc_valid; // Indicates that a new trace PC is valid
210	reg trace_pc_valid;
211	output trace_exception; // Indicates an exception has occured
212	reg trace_exception;
213	output [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
214	reg [`LM32_EID_RNG] trace_eid;
215	output trace_eret; // Indicates an eret instruction has been executed
216	reg trace_eret;
217	`ifdef CFG_DEBUG_ENABLED
218	output trace_bret; // Indicates a bret instruction has been executed
219	reg trace_bret;
220	`endif
221	`endif
222
223	`ifdef CFG_JTAG_ENABLED
224	output [`LM32_BYTE_RNG] jtag_reg_d;
225	wire [`LM32_BYTE_RNG] jtag_reg_d;
226	output [2:0] jtag_reg_addr_d;
227	wire [2:0] jtag_reg_addr_d;
228	`endif
229
230	`ifdef CFG_USER_ENABLED
231	output user_valid; // Indicates if user_opcode is valid
232	wire user_valid;
233	output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
234	reg [`LM32_USER_OPCODE_RNG] user_opcode;
235	output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
236	wire [`LM32_WORD_RNG] user_operand_0;
237	output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
238	wire [`LM32_WORD_RNG] user_operand_1;
239	`endif
240
241	`ifdef CFG_IWB_ENABLED
242	output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
243	wire [`LM32_WORD_RNG] I_DAT_O;
244	output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
245	wire [`LM32_WORD_RNG] I_ADR_O;
246	output I_CYC_O; // Instruction Wishbone interface cycle
247	wire I_CYC_O;
248	output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
249	wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
250	output I_STB_O; // Instruction Wishbone interface strobe
251	wire I_STB_O;
252	output I_WE_O; // Instruction Wishbone interface write enable
253	wire I_WE_O;
254	output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
255	wire [`LM32_CTYPE_RNG] I_CTI_O;
256	output I_LOCK_O; // Instruction Wishbone interface lock bus
257	wire I_LOCK_O;
258	output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
259	wire [`LM32_BTYPE_RNG] I_BTE_O;
260	`endif
261
262	output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
263	wire [`LM32_WORD_RNG] D_DAT_O;
264	output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
265	wire [`LM32_WORD_RNG] D_ADR_O;
266	output D_CYC_O; // Data Wishbone interface cycle
267	wire D_CYC_O;
268	output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
269	wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
270	output D_STB_O; // Data Wishbone interface strobe
271	wire D_STB_O;
272	output D_WE_O; // Data Wishbone interface write enable
273	wire D_WE_O;
274	output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
275	wire [`LM32_CTYPE_RNG] D_CTI_O;
276	output D_LOCK_O; // Date Wishbone interface lock bus
277	wire D_LOCK_O;
278	output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
279	wire [`LM32_BTYPE_RNG] D_BTE_O;
280
281	/////////////////////////////////////////////////////
282	// Internal nets and registers
283	/////////////////////////////////////////////////////
284
285	// Pipeline registers
286
287	`ifdef LM32_CACHE_ENABLED
288	reg valid_a; // Instruction in A stage is valid
289	`endif
290	reg valid_f; // Instruction in F stage is valid
291	reg valid_d; // Instruction in D stage is valid
292	reg valid_x; // Instruction in X stage is valid
293	reg valid_m; // Instruction in M stage is valid
294	reg valid_w; // Instruction in W stage is valid
295
296	wire [`LM32_WORD_RNG] immediate_d; // Immediate operand
297	wire load_d; // Indicates a load instruction
298	reg load_x;
299	reg load_m;
300	wire store_d; // Indicates a store instruction
301	reg store_x;
302	reg store_m;
303	wire [`LM32_SIZE_RNG] size_d; // Size of load/store (byte, hword, word)
304	reg [`LM32_SIZE_RNG] size_x;
305	wire branch_d; // Indicates a branch instruction
306	reg branch_x;
307	reg branch_m;
308	wire branch_reg_d; // Branch to register or immediate
309	wire [`LM32_PC_RNG] branch_offset_d; // Branch offset for immediate branches
310	reg [`LM32_PC_RNG] branch_target_x; // Address to branch to
311	reg [`LM32_PC_RNG] branch_target_m;
312	wire [`LM32_D_RESULT_SEL_0_RNG] d_result_sel_0_d; // Which result should be selected in D stage for operand 0
313	wire [`LM32_D_RESULT_SEL_1_RNG] d_result_sel_1_d; // Which result should be selected in D stage for operand 1
314
315	wire x_result_sel_csr_d; // Select X stage result from CSRs
316	reg x_result_sel_csr_x;
317	`ifdef LM32_MC_ARITHMETIC_ENABLED
318	wire x_result_sel_mc_arith_d; // Select X stage result from multi-cycle arithmetic unit
319	reg x_result_sel_mc_arith_x;
320	`endif
321	`ifdef LM32_NO_BARREL_SHIFT
322	wire x_result_sel_shift_d; // Select X stage result from shifter
323	reg x_result_sel_shift_x;
324	`endif
325	`ifdef CFG_SIGN_EXTEND_ENABLED
326	wire x_result_sel_sext_d; // Select X stage result from sign-extend logic
327	reg x_result_sel_sext_x;
328	`endif
329	wire x_result_sel_logic_d; // Select X stage result from logic op unit
330	reg x_result_sel_logic_x;
331	`ifdef CFG_USER_ENABLED
332	wire x_result_sel_user_d; // Select X stage result from user-defined logic
333	reg x_result_sel_user_x;
334	`endif
335	wire x_result_sel_add_d; // Select X stage result from adder
336	reg x_result_sel_add_x;
337	wire m_result_sel_compare_d; // Select M stage result from comparison logic
338	reg m_result_sel_compare_x;
339	reg m_result_sel_compare_m;
340	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
341	wire m_result_sel_shift_d; // Select M stage result from shifter
342	reg m_result_sel_shift_x;
343	reg m_result_sel_shift_m;
344	`endif
345	wire w_result_sel_load_d; // Select W stage result from load/store unit
346	reg w_result_sel_load_x;
347	reg w_result_sel_load_m;
348	reg w_result_sel_load_w;
349	`ifdef CFG_PL_MULTIPLY_ENABLED
350	wire w_result_sel_mul_d; // Select W stage result from multiplier
351	reg w_result_sel_mul_x;
352	reg w_result_sel_mul_m;
353	reg w_result_sel_mul_w;
354	`endif
355	wire x_bypass_enable_d; // Whether result is bypassable in X stage
356	reg x_bypass_enable_x;
357	wire m_bypass_enable_d; // Whether result is bypassable in M stage
358	reg m_bypass_enable_x;
359	reg m_bypass_enable_m;
360	wire sign_extend_d; // Whether to sign-extend or zero-extend
361	reg sign_extend_x;
362	wire write_enable_d; // Register file write enable
363	reg write_enable_x;
364	wire write_enable_q_x;
365	reg write_enable_m;
366	wire write_enable_q_m;
367	reg write_enable_w;
368	wire write_enable_q_w;
369	wire read_enable_0_d; // Register file read enable 0
370	wire [`LM32_REG_IDX_RNG] read_idx_0_d; // Register file read index 0
371	wire read_enable_1_d; // Register file read enable 1
372	wire [`LM32_REG_IDX_RNG] read_idx_1_d; // Register file read index 1
373	wire [`LM32_REG_IDX_RNG] write_idx_d; // Register file write index
374	reg [`LM32_REG_IDX_RNG] write_idx_x;
375	reg [`LM32_REG_IDX_RNG] write_idx_m;
376	reg [`LM32_REG_IDX_RNG] write_idx_w;
377	wire [`LM32_CSR_RNG] csr_d; // CSR read/write index
378	reg [`LM32_CSR_RNG] csr_x;
379	wire [`LM32_CONDITION_RNG] condition_d; // Branch condition
380	reg [`LM32_CONDITION_RNG] condition_x;
381	`ifdef CFG_DEBUG_ENABLED
382	wire break_d; // Indicates a break instruction
383	reg break_x;
384	`endif
385	wire scall_d; // Indicates a scall instruction
386	reg scall_x;
387	wire eret_d; // Indicates an eret instruction
388	reg eret_x;
389	wire eret_q_x;
390	reg eret_m;
391	`ifdef CFG_TRACE_ENABLED
392	reg eret_w;
393	`endif
394	`ifdef CFG_DEBUG_ENABLED
395	wire bret_d; // Indicates a bret instruction
396	reg bret_x;
397	wire bret_q_x;
398	reg bret_m;
399	`ifdef CFG_TRACE_ENABLED
400	reg bret_w;
401	`endif
402	`endif
403	wire csr_write_enable_d; // CSR write enable
404	reg csr_write_enable_x;
405	wire csr_write_enable_q_x;
406	`ifdef CFG_USER_ENABLED
407	wire [`LM32_USER_OPCODE_RNG] user_opcode_d; // User-defined instruction opcode
408	`endif
409
410	`ifdef CFG_BUS_ERRORS_ENABLED
411	wire bus_error_d; // Indicates an bus error occured while fetching the instruction in this pipeline stage
412	reg bus_error_x;
413	`endif
414
415	reg [`LM32_WORD_RNG] d_result_0; // Result of instruction in D stage (operand 0)
416	reg [`LM32_WORD_RNG] d_result_1; // Result of instruction in D stage (operand 1)
417	reg [`LM32_WORD_RNG] x_result; // Result of instruction in X stage
418	reg [`LM32_WORD_RNG] m_result; // Result of instruction in M stage
419	reg [`LM32_WORD_RNG] w_result; // Result of instruction in W stage
420
421	reg [`LM32_WORD_RNG] operand_0_x; // Operand 0 for X stage instruction
422	reg [`LM32_WORD_RNG] operand_1_x; // Operand 1 for X stage instruction
423	reg [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
424	reg [`LM32_WORD_RNG] operand_m; // Operand for M stage instruction
425	reg [`LM32_WORD_RNG] operand_w; // Operand for W stage instruction
426
427	// To/from register file
428	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
429	wire [`LM32_WORD_RNG] reg_data_live_0;
430	wire [`LM32_WORD_RNG] reg_data_live_1;
431	reg use_buf; // Whether to use reg_data_live or reg_data_buf
432	reg [`LM32_WORD_RNG] reg_data_buf_0;
433	reg [`LM32_WORD_RNG] reg_data_buf_1;
434	`endif
435	`ifdef LM32_EBR_REGISTER_FILE
436	`else
437	reg [`LM32_WORD_RNG] registers[0:(1<<`LM32_REG_IDX_WIDTH)-1]; // Register file
438	`endif
439	wire [`LM32_WORD_RNG] reg_data_0; // Register file read port 0 data
440	wire [`LM32_WORD_RNG] reg_data_1; // Register file read port 1 data
441	reg [`LM32_WORD_RNG] bypass_data_0; // Register value 0 after bypassing
442	reg [`LM32_WORD_RNG] bypass_data_1; // Register value 1 after bypassing
443	wire reg_write_enable_q_w;
444
445	reg interlock; // Indicates pipeline should be stalled because of a read-after-write hazzard
446
447	wire stall_a; // Stall instruction in A pipeline stage
448	wire stall_f; // Stall instruction in F pipeline stage
449	wire stall_d; // Stall instruction in D pipeline stage
450	wire stall_x; // Stall instruction in X pipeline stage
451	wire stall_m; // Stall instruction in M pipeline stage
452
453	// To/from adder
454	wire adder_op_d; // Whether to add or subtract
455	reg adder_op_x;
456	reg adder_op_x_n; // Inverted version of adder_op_x
457	wire [`LM32_WORD_RNG] adder_result_x; // Result from adder
458	wire adder_overflow_x; // Whether a signed overflow occured
459	wire adder_carry_n_x; // Whether a carry was generated
460
461	// To/from logical operations unit
462	wire [`LM32_LOGIC_OP_RNG] logic_op_d; // Which operation to perform
463	reg [`LM32_LOGIC_OP_RNG] logic_op_x;
464	wire [`LM32_WORD_RNG] logic_result_x; // Result of logical operation
465
466	`ifdef CFG_SIGN_EXTEND_ENABLED
467	// From sign-extension unit
468	wire [`LM32_WORD_RNG] sextb_result_x; // Result of byte sign-extension
469	wire [`LM32_WORD_RNG] sexth_result_x; // Result of half-word sign-extenstion
470	wire [`LM32_WORD_RNG] sext_result_x; // Result of sign-extension specified by instruction
471	`endif
472
473	// To/from shifter
474	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
475	`ifdef CFG_ROTATE_ENABLED
476	wire rotate_d; // Whether we should rotate or shift
477	reg rotate_x;
478	`endif
479	wire direction_d; // Which direction to shift in
480	reg direction_x;
481	reg direction_m;
482	wire [`LM32_WORD_RNG] shifter_result_m; // Result of shifter
483	`endif
484	`ifdef CFG_MC_BARREL_SHIFT_ENABLED
485	wire shift_left_d; // Indicates whether to perform a left shift or not
486	wire shift_left_q_d;
487	wire shift_right_d; // Indicates whether to perform a right shift or not
488	wire shift_right_q_d;
489	`endif
490	`ifdef LM32_NO_BARREL_SHIFT
491	wire [`LM32_WORD_RNG] shifter_result_x; // Result of single-bit right shifter
492	`endif
493
494	// To/from multiplier
495	`ifdef LM32_MULTIPLY_ENABLED
496	wire [`LM32_WORD_RNG] multiplier_result_w; // Result from multiplier
497	`endif
498	`ifdef CFG_MC_MULTIPLY_ENABLED
499	wire multiply_d; // Indicates whether to perform a multiply or not
500	wire multiply_q_d;
501	`endif
502
503	// To/from divider
504	`ifdef CFG_MC_DIVIDE_ENABLED
505	wire divide_d; // Indicates whether to perform a divider or not
506	wire divide_q_d;
507	wire modulus_d;
508	wire modulus_q_d;
509	wire divide_by_zero_x; // Indicates an attempt was made to divide by zero
510	`endif
511
512	// To from multi-cycle arithmetic unit
513	`ifdef LM32_MC_ARITHMETIC_ENABLED
514	wire mc_stall_request_x; // Multi-cycle arithmetic unit stall request
515	wire [`LM32_WORD_RNG] mc_result_x;
516	`endif
517
518	// From CSRs
519	`ifdef CFG_INTERRUPTS_ENABLED
520	wire [`LM32_WORD_RNG] interrupt_csr_read_data_x;// Data read from interrupt CSRs
521	`endif
522	wire [`LM32_WORD_RNG] cfg; // Configuration CSR
523	`ifdef CFG_CYCLE_COUNTER_ENABLED
524	reg [`LM32_WORD_RNG] cc; // Cycle counter CSR
525	`endif
526	reg [`LM32_WORD_RNG] csr_read_data_x; // Data read from CSRs
527
528	// To/from instruction unit
529	wire [`LM32_PC_RNG] pc_f; // PC of instruction in F stage
530	wire [`LM32_PC_RNG] pc_d; // PC of instruction in D stage
531	wire [`LM32_PC_RNG] pc_x; // PC of instruction in X stage
532	wire [`LM32_PC_RNG] pc_m; // PC of instruction in M stage
533	wire [`LM32_PC_RNG] pc_w; // PC of instruction in W stage
534	`ifdef CFG_TRACE_ENABLED
535	reg [`LM32_PC_RNG] pc_c; // PC of last commited instruction
536	`endif
537	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
538	wire [`LM32_INSTRUCTION_RNG] instruction_f; // Instruction in F stage
539	`endif
540	wire [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction in D stage
541	`ifdef CFG_ICACHE_ENABLED
542	wire iflush; // Flush instruction cache
543	wire icache_stall_request; // Stall pipeline because instruction cache is busy
544	wire icache_restart_request; // Restart instruction that caused an instruction cache miss
545	wire icache_refill_request; // Request to refill instruction cache
546	wire icache_refilling; // Indicates the instruction cache is being refilled
547	`endif
548
549	// To/from load/store unit
550	`ifdef CFG_DCACHE_ENABLED
551	wire dflush_x; // Flush data cache
552	reg dflush_m;
553	wire dcache_stall_request; // Stall pipeline because data cache is busy
554	wire dcache_restart_request; // Restart instruction that caused a data cache miss
555	wire dcache_refill_request; // Request to refill data cache
556	wire dcache_refilling; // Indicates the data cache is being refilled
557	`endif
558	wire [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
559	wire stall_wb_load; // Stall pipeline because of a load via the data Wishbone interface
560
561	// To/from JTAG interface
562	`ifdef CFG_JTAG_ENABLED
563	`ifdef CFG_JTAG_UART_ENABLED
564	wire [`LM32_WORD_RNG] jtx_csr_read_data; // Read data for JTX CSR
565	wire [`LM32_WORD_RNG] jrx_csr_read_data; // Read data for JRX CSR
566	`endif
567	`ifdef CFG_HW_DEBUG_ENABLED
568	wire jtag_csr_write_enable; // Debugger CSR write enable
569	wire [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
570	wire [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
571	wire jtag_read_enable;
572	wire [`LM32_BYTE_RNG] jtag_read_data;
573	wire jtag_write_enable;
574	wire [`LM32_BYTE_RNG] jtag_write_data;
575	wire [`LM32_WORD_RNG] jtag_address;
576	wire jtag_access_complete;
577	`endif
578	`ifdef CFG_DEBUG_ENABLED
579	wire jtag_break; // Request from debugger to raise a breakpoint
580	`endif
581	`endif
582
583	// Hazzard detection
584	wire raw_x_0; // RAW hazzard between instruction in X stage and read port 0
585	wire raw_x_1; // RAW hazzard between instruction in X stage and read port 1
586	wire raw_m_0; // RAW hazzard between instruction in M stage and read port 0
587	wire raw_m_1; // RAW hazzard between instruction in M stage and read port 1
588	wire raw_w_0; // RAW hazzard between instruction in W stage and read port 0
589	wire raw_w_1; // RAW hazzard between instruction in W stage and read port 1
590
591	// Control flow
592	wire cmp_zero; // Result of comparison is zero
593	wire cmp_negative; // Result of comparison is negative
594	wire cmp_overflow; // Comparison produced an overflow
595	wire cmp_carry_n; // Comparison produced a carry, inverted
596	reg condition_met_x; // Condition of branch instruction is met
597	reg condition_met_m;
598	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
599	wire branch_taken_x; // Branch is taken in X stage
600	`endif
601	wire branch_taken_m; // Branch is taken in M stage
602
603	wire kill_f; // Kill instruction in F stage
604	wire kill_d; // Kill instruction in D stage
605	wire kill_x; // Kill instruction in X stage
606	wire kill_m; // Kill instruction in M stage
607	wire kill_w; // Kill instruction in W stage
608
609	reg [`LM32_PC_WIDTH+2-1:8] eba; // Exception Base Address (EBA) CSR
610	`ifdef CFG_DEBUG_ENABLED
611	reg [`LM32_PC_WIDTH+2-1:8] deba; // Debug Exception Base Address (DEBA) CSR
612	`endif
613	reg [`LM32_EID_RNG] eid_x; // Exception ID in X stage
614	`ifdef CFG_TRACE_ENABLED
615	reg [`LM32_EID_RNG] eid_m; // Exception ID in M stage
616	reg [`LM32_EID_RNG] eid_w; // Exception ID in W stage
617	`endif
618
619	`ifdef CFG_DEBUG_ENABLED
620	`ifdef LM32_SINGLE_STEP_ENABLED
621	wire dc_ss; // Is single-step enabled
622	`endif
623	wire dc_re; // Remap all exceptions
624	wire exception_x; // An exception occured in the X stage
625	reg exception_m; // An instruction that caused an exception is in the M stage
626	wire debug_exception_x; // Indicates if a debug exception has occured
627	reg debug_exception_m;
628	reg debug_exception_w;
629	wire debug_exception_q_w;
630	wire non_debug_exception_x; // Indicates if a non debug exception has occured
631	reg non_debug_exception_m;
632	reg non_debug_exception_w;
633	wire non_debug_exception_q_w;
634	`else
635	wire exception_x; // Indicates if a debug exception has occured
636	reg exception_m;
637	reg exception_w;
638	wire exception_q_w;
639	`endif
640
641	`ifdef CFG_DEBUG_ENABLED
642	`ifdef CFG_JTAG_ENABLED
643	wire reset_exception; // Indicates if a reset exception has occured
644	`endif
645	`endif
646	`ifdef CFG_INTERRUPTS_ENABLED
647	wire interrupt_exception; // Indicates if an interrupt exception has occured
648	`endif
649	`ifdef CFG_DEBUG_ENABLED
650	wire breakpoint_exception; // Indicates if a breakpoint exception has occured
651	wire watchpoint_exception; // Indicates if a watchpoint exception has occured
652	`endif
653	`ifdef CFG_BUS_ERRORS_ENABLED
654	wire instruction_bus_error_exception; // Indicates if an instruction bus error exception has occured
655	wire data_bus_error_exception; // Indicates if a data bus error exception has occured
656	`endif
657	`ifdef CFG_MC_DIVIDE_ENABLED
658	wire divide_by_zero_exception; // Indicates if a divide by zero exception has occured
659	`endif
660	wire system_call_exception; // Indicates if a system call exception has occured
661
662	`ifdef CFG_BUS_ERRORS_ENABLED
663	reg data_bus_error_seen; // Indicates if a data bus error was seen
664	`endif
665
666	/////////////////////////////////////////////////////
667	// Functions
668	/////////////////////////////////////////////////////
669
670	`include "lm32_functions.v"
671
672	/////////////////////////////////////////////////////
673	// Instantiations
674	/////////////////////////////////////////////////////
675
676	// Instruction unit
677	lm32_instruction_unit #(
678	.associativity (icache_associativity),
679	.sets (icache_sets),
680	.bytes_per_line (icache_bytes_per_line),
681	.base_address (icache_base_address),
682	.limit (icache_limit)
683	) instruction_unit (
684	// ----- Inputs -------
685	.clk_i (clk_i),
686	.rst_i (rst_i),
687	// From pipeline
688	.stall_a (stall_a),
689	.stall_f (stall_f),
690	.stall_d (stall_d),
691	.stall_x (stall_x),
692	.stall_m (stall_m),
693	.valid_f (valid_f),
694	.kill_f (kill_f),
695	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
696	.branch_taken_x (branch_taken_x),
697	.branch_target_x (branch_target_x),
698	`endif
699	.branch_taken_m (branch_taken_m),
700	.branch_target_m (branch_target_m),
701	`ifdef CFG_ICACHE_ENABLED
702	.iflush (iflush),
703	`endif
704	`ifdef CFG_DCACHE_ENABLED
705	.dcache_restart_request (dcache_restart_request),
706	.dcache_refill_request (dcache_refill_request),
707	.dcache_refilling (dcache_refilling),
708	`endif
709	`ifdef CFG_IWB_ENABLED
710	// From Wishbone
711	.i_dat_i (I_DAT_I),
712	.i_ack_i (I_ACK_I),
713	.i_err_i (I_ERR_I),
714	.i_rty_i (I_RTY_I),
715	`endif
716	`ifdef CFG_HW_DEBUG_ENABLED
717	.jtag_read_enable (jtag_read_enable),
718	.jtag_write_enable (jtag_write_enable),
719	.jtag_write_data (jtag_write_data),
720	.jtag_address (jtag_address),
721	`endif
722	// ----- Outputs -------
723	// To pipeline
724	.pc_f (pc_f),
725	.pc_d (pc_d),
726	.pc_x (pc_x),
727	.pc_m (pc_m),
728	.pc_w (pc_w),
729	`ifdef CFG_ICACHE_ENABLED
730	.icache_stall_request (icache_stall_request),
731	.icache_restart_request (icache_restart_request),
732	.icache_refill_request (icache_refill_request),
733	.icache_refilling (icache_refilling),
734	`endif
735	`ifdef CFG_IWB_ENABLED
736	// To Wishbone
737	.i_dat_o (I_DAT_O),
738	.i_adr_o (I_ADR_O),
739	.i_cyc_o (I_CYC_O),
740	.i_sel_o (I_SEL_O),
741	.i_stb_o (I_STB_O),
742	.i_we_o (I_WE_O),
743	.i_cti_o (I_CTI_O),
744	.i_lock_o (I_LOCK_O),
745	.i_bte_o (I_BTE_O),
746	`endif
747	`ifdef CFG_HW_DEBUG_ENABLED
748	.jtag_read_data (jtag_read_data),
749	.jtag_access_complete (jtag_access_complete),
750	`endif
751	`ifdef CFG_BUS_ERRORS_ENABLED
752	.bus_error_d (bus_error_d),
753	`endif
754	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
755	.instruction_f (instruction_f),
756	`endif
757	.instruction_d (instruction_d)
758	);
759
760	// Trace instructions in simulation
761	lm32_simtrace simtrace (
762	.clk_i (clk_i),
763	.rst_i (rst_i),
764	.stall_x (stall_x),
765	.stall_m (stall_m),
766	.valid_w (valid_w),
767	.kill_w (kill_w),
768	.instruction_d (instruction_d),
769	.pc_w (pc_w)
770	);
771
772	// Instruction decoder
773	lm32_decoder decoder (
774	// ----- Inputs -------
775	.instruction (instruction_d),
776	// ----- Outputs -------
777	.d_result_sel_0 (d_result_sel_0_d),
778	.d_result_sel_1 (d_result_sel_1_d),
779	.x_result_sel_csr (x_result_sel_csr_d),
780	`ifdef LM32_MC_ARITHMETIC_ENABLED
781	.x_result_sel_mc_arith (x_result_sel_mc_arith_d),
782	`endif
783	`ifdef LM32_NO_BARREL_SHIFT
784	.x_result_sel_shift (x_result_sel_shift_d),
785	`endif
786	`ifdef CFG_SIGN_EXTEND_ENABLED
787	.x_result_sel_sext (x_result_sel_sext_d),
788	`endif
789	.x_result_sel_logic (x_result_sel_logic_d),
790	`ifdef CFG_USER_ENABLED
791	.x_result_sel_user (x_result_sel_user_d),
792	`endif
793	.x_result_sel_add (x_result_sel_add_d),
794	.m_result_sel_compare (m_result_sel_compare_d),
795	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
796	.m_result_sel_shift (m_result_sel_shift_d),
797	`endif
798	.w_result_sel_load (w_result_sel_load_d),
799	`ifdef CFG_PL_MULTIPLY_ENABLED
800	.w_result_sel_mul (w_result_sel_mul_d),
801	`endif
802	.x_bypass_enable (x_bypass_enable_d),
803	.m_bypass_enable (m_bypass_enable_d),
804	.read_enable_0 (read_enable_0_d),
805	.read_idx_0 (read_idx_0_d),
806	.read_enable_1 (read_enable_1_d),
807	.read_idx_1 (read_idx_1_d),
808	.write_enable (write_enable_d),
809	.write_idx (write_idx_d),
810	.immediate (immediate_d),
811	.branch_offset (branch_offset_d),
812	.load (load_d),
813	.store (store_d),
814	.size (size_d),
815	.sign_extend (sign_extend_d),
816	.adder_op (adder_op_d),
817	.logic_op (logic_op_d),
818	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
819	.direction (direction_d),
820	`endif
821	`ifdef CFG_MC_BARREL_SHIFT_ENABLED
822	.shift_left (shift_left_d),
823	.shift_right (shift_right_d),
824	`endif
825	`ifdef CFG_MC_MULTIPLY_ENABLED
826	.multiply (multiply_d),
827	`endif
828	`ifdef CFG_MC_DIVIDE_ENABLED
829	.divide (divide_d),
830	.modulus (modulus_d),
831	`endif
832	.branch (branch_d),
833	.branch_reg (branch_reg_d),
834	.condition (condition_d),
835	`ifdef CFG_DEBUG_ENABLED
836	.break (break_d),
837	`endif
838	.scall (scall_d),
839	.eret (eret_d),
840	`ifdef CFG_DEBUG_ENABLED
841	.bret (bret_d),
842	`endif
843	`ifdef CFG_USER_ENABLED
844	.user_opcode (user_opcode_d),
845	`endif
846	.csr_write_enable (csr_write_enable_d)
847	);
848
849	// Load/store unit
850	lm32_load_store_unit #(
851	.associativity (dcache_associativity),
852	.sets (dcache_sets),
853	.bytes_per_line (dcache_bytes_per_line),
854	.base_address (dcache_base_address),
855	.limit (dcache_limit)
856	) load_store_unit (
857	// ----- Inputs -------
858	.clk_i (clk_i),
859	.rst_i (rst_i),
860	// From pipeline
861	.stall_a (stall_a),
862	.stall_x (stall_x),
863	.stall_m (stall_m),
864	.kill_x (kill_x),
865	.kill_m (kill_m),
866	.exception_m (exception_m),
867	.store_operand_x (store_operand_x),
868	.load_store_address_x (adder_result_x),
869	.load_store_address_m (operand_m),
870	.load_store_address_w (operand_w[1:0]),
871	.load_q_x (load_q_x),
872	.load_q_m (load_q_m),
873	.store_q_m (store_q_m),
874	.sign_extend_x (sign_extend_x),
875	.size_x (size_x),
876	`ifdef CFG_DCACHE_ENABLED
877	.dflush (dflush_m),
878	`endif
879	// From Wishbone
880	.d_dat_i (D_DAT_I),
881	.d_ack_i (D_ACK_I),
882	.d_err_i (D_ERR_I),
883	.d_rty_i (D_RTY_I),
884	// ----- Outputs -------
885	// To pipeline
886	`ifdef CFG_DCACHE_ENABLED
887	.dcache_refill_request (dcache_refill_request),
888	.dcache_restart_request (dcache_restart_request),
889	.dcache_stall_request (dcache_stall_request),
890	.dcache_refilling (dcache_refilling),
891	`endif
892	.load_data_w (load_data_w),
893	.stall_wb_load (stall_wb_load),
894	// To Wishbone
895	.d_dat_o (D_DAT_O),
896	.d_adr_o (D_ADR_O),
897	.d_cyc_o (D_CYC_O),
898	.d_sel_o (D_SEL_O),
899	.d_stb_o (D_STB_O),
900	.d_we_o (D_WE_O),
901	.d_cti_o (D_CTI_O),
902	.d_lock_o (D_LOCK_O),
903	.d_bte_o (D_BTE_O)
904	);
905
906	// Adder
907	lm32_adder adder (
908	// ----- Inputs -------
909	.adder_op_x (adder_op_x),
910	.adder_op_x_n (adder_op_x_n),
911	.operand_0_x (operand_0_x),
912	.operand_1_x (operand_1_x),
913	// ----- Outputs -------
914	.adder_result_x (adder_result_x),
915	.adder_carry_n_x (adder_carry_n_x),
916	.adder_overflow_x (adder_overflow_x)
917	);
918
919	// Logic operations
920	lm32_logic_op logic_op (
921	// ----- Inputs -------
922	.logic_op_x (logic_op_x),
923	.operand_0_x (operand_0_x),
924
925	.operand_1_x (operand_1_x),
926	// ----- Outputs -------
927	.logic_result_x (logic_result_x)
928	);
929
930	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
931	// Pipelined barrel-shifter
932	lm32_shifter shifter (
933	// ----- Inputs -------
934	.clk_i (clk_i),
935	.rst_i (rst_i),
936	.stall_x (stall_x),
937	.direction_x (direction_x),
938	.sign_extend_x (sign_extend_x),
939	.operand_0_x (operand_0_x),
940	.operand_1_x (operand_1_x),
941	// ----- Outputs -------
942	.shifter_result_m (shifter_result_m)
943	);
944	`endif
945
946	`ifdef CFG_PL_MULTIPLY_ENABLED
947	// Pipeline fixed-point multiplier
948	lm32_multiplier multiplier (
949	// ----- Inputs -------
950	.clk_i (clk_i),
951	.rst_i (rst_i),
952	.stall_x (stall_x),
953	.stall_m (stall_m),
954	.operand_0 (d_result_0),
955	.operand_1 (d_result_1),
956	// ----- Outputs -------
957	.result (multiplier_result_w)
958	);
959	`endif
960
961	`ifdef LM32_MC_ARITHMETIC_ENABLED
962	// Multi-cycle arithmetic
963	lm32_mc_arithmetic mc_arithmetic (
964	// ----- Inputs -------
965	.clk_i (clk_i),
966	.rst_i (rst_i),
967	.stall_d (stall_d),
968	.kill_x (kill_x),
969	`ifdef CFG_MC_DIVIDE_ENABLED
970	.divide_d (divide_q_d),
971	.modulus_d (modulus_q_d),
972	`endif
973	`ifdef CFG_MC_MULTIPLY_ENABLED
974	.multiply_d (multiply_q_d),
975	`endif
976	`ifdef CFG_MC_BARREL_SHIFT_ENABLED
977	.shift_left_d (shift_left_q_d),
978	.shift_right_d (shift_right_q_d),
979	.sign_extend_d (sign_extend_d),
980	`endif
981	.operand_0_d (d_result_0),
982	.operand_1_d (d_result_1),
983	// ----- Outputs -------
984	.result_x (mc_result_x),
985	`ifdef CFG_MC_DIVIDE_ENABLED
986	.divide_by_zero_x (divide_by_zero_x),
987	`endif
988	.stall_request_x (mc_stall_request_x)
989	);
990	`endif
991
992	`ifdef CFG_INTERRUPTS_ENABLED
993	// Interrupt unit
994	lm32_interrupt interrupt (
995	// ----- Inputs -------
996	.clk_i (clk_i),
997	.rst_i (rst_i),
998	// From external devices
999	.interrupt_n (interrupt_n),
1000	// From pipeline
1001	.stall_x (stall_x),
1002	`ifdef CFG_DEBUG_ENABLED
1003	.non_debug_exception (non_debug_exception_q_w),
1004	.debug_exception (debug_exception_q_w),
1005	`else
1006	.exception (exception_q_w),
1007	`endif
1008	.eret_q_x (eret_q_x),
1009	`ifdef CFG_DEBUG_ENABLED
1010	.bret_q_x (bret_q_x),
1011	`endif
1012	.csr (csr_x),
1013	.csr_write_data (operand_1_x),
1014	.csr_write_enable (csr_write_enable_q_x),
1015	// ----- Outputs -------
1016	.interrupt_exception (interrupt_exception),
1017	// To pipeline
1018	.csr_read_data (interrupt_csr_read_data_x)
1019	);
1020	`endif
1021
1022	`ifdef CFG_JTAG_ENABLED
1023	// JTAG interface
1024	lm32_jtag jtag (
1025	// ----- Inputs -------
1026	.clk_i (clk_i),
1027	.rst_i (rst_i),
1028	// From JTAG
1029	.jtag_clk (jtag_clk),
1030	.jtag_update (jtag_update),
1031	.jtag_reg_q (jtag_reg_q),
1032	.jtag_reg_addr_q (jtag_reg_addr_q),
1033	// From pipeline
1034	`ifdef CFG_JTAG_UART_ENABLED
1035	.csr (csr_x),
1036	.csr_write_data (operand_1_x),
1037	.csr_write_enable (csr_write_enable_q_x),
1038	.stall_x (stall_x),
1039	`endif
1040	`ifdef CFG_HW_DEBUG_ENABLED
1041	.jtag_read_data (jtag_read_data),
1042	.jtag_access_complete (jtag_access_complete),
1043	`endif
1044	`ifdef CFG_DEBUG_ENABLED
1045	.exception_q_w (debug_exception_q_w \|\| non_debug_exception_q_w),
1046	`endif
1047	// ----- Outputs -------
1048	// To pipeline
1049	`ifdef CFG_JTAG_UART_ENABLED
1050	.jtx_csr_read_data (jtx_csr_read_data),
1051	.jrx_csr_read_data (jrx_csr_read_data),
1052	`endif
1053	`ifdef CFG_HW_DEBUG_ENABLED
1054	.jtag_csr_write_enable (jtag_csr_write_enable),
1055	.jtag_csr_write_data (jtag_csr_write_data),
1056	.jtag_csr (jtag_csr),
1057	.jtag_read_enable (jtag_read_enable),
1058	.jtag_write_enable (jtag_write_enable),
1059	.jtag_write_data (jtag_write_data),
1060	.jtag_address (jtag_address),
1061	`endif
1062	`ifdef CFG_DEBUG_ENABLED
1063	.jtag_break (jtag_break),
1064	.jtag_reset (reset_exception),
1065	`endif
1066	// To JTAG
1067	.jtag_reg_d (jtag_reg_d),
1068	.jtag_reg_addr_d (jtag_reg_addr_d)
1069	);
1070	`endif
1071
1072	`ifdef CFG_DEBUG_ENABLED
1073	// Debug unit
1074	lm32_debug #(
1075	.breakpoints (breakpoints),
1076	.watchpoints (watchpoints)
1077	) hw_debug (
1078	// ----- Inputs -------
1079	.clk_i (clk_i),
1080	.rst_i (rst_i),
1081	.pc_x (pc_x),
1082	.load_x (load_x),
1083	.store_x (store_x),
1084	.load_store_address_x (adder_result_x),
1085	.csr_write_enable_x (csr_write_enable_q_x),
1086	.csr_write_data (operand_1_x),
1087	.csr_x (csr_x),
1088	`ifdef CFG_HW_DEBUG_ENABLED
1089	.jtag_csr_write_enable (jtag_csr_write_enable),
1090	.jtag_csr_write_data (jtag_csr_write_data),
1091	.jtag_csr (jtag_csr),
1092	`endif
1093	`ifdef LM32_SINGLE_STEP_ENABLED
1094	.eret_q_x (eret_q_x),
1095	.bret_q_x (bret_q_x),
1096	.stall_x (stall_x),
1097	.exception_x (exception_x),
1098	.q_x (q_x),
1099	`ifdef CFG_DCACHE_ENABLED
1100	.dcache_refill_request (dcache_refill_request),
1101	`endif
1102	`endif
1103	// ----- Outputs -------
1104	`ifdef LM32_SINGLE_STEP_ENABLED
1105	.dc_ss (dc_ss),
1106	`endif
1107	.dc_re (dc_re),
1108	.bp_match (bp_match),
1109	.wp_match (wp_match)
1110	);
1111	`endif
1112
1113	// Register file
1114
1115	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1116
1117	lm32_ram #(
1118	// ----- Parameters -------
1119	.data_width (`LM32_WORD_WIDTH),
1120	.address_width (`LM32_REG_IDX_WIDTH)
1121	) reg_0 (
1122	// ----- Inputs -------
1123	.read_clk (clk_i),
1124	.write_clk (clk_i),
1125	.reset (rst_i),
1126	.enable_read (stall_d == `FALSE),
1127	.read_address (instruction_f[25:21]),
1128	.enable_write (`TRUE),
1129	.write_address (write_idx_w),
1130	.write_data (w_result),
1131	.write_enable (reg_write_enable_q_w),
1132	// ----- Outputs -------
1133	.read_data (reg_data_live_0)
1134	);
1135
1136	lm32_ram #(
1137	// ----- Parameters -------
1138	.data_width (`LM32_WORD_WIDTH),
1139	.address_width (`LM32_REG_IDX_WIDTH)
1140	) reg_1 (
1141	// ----- Inputs -------
1142	.read_clk (clk_i),
1143	.write_clk (clk_i),
1144	.reset (rst_i),
1145	.enable_read (stall_d == `FALSE),
1146	.read_address (instruction_f[20:16]),
1147	.enable_write (`TRUE),
1148	.write_address (write_idx_w),
1149	.write_data (w_result),
1150	.write_enable (reg_write_enable_q_w),
1151	// ----- Outputs -------
1152	.read_data (reg_data_live_1)
1153	);
1154
1155	`endif
1156
1157	`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
1158
1159	lm32_ram #(
1160	// ----- Parameters -------
1161	.data_width (`LM32_WORD_WIDTH),
1162	.address_width (`LM32_REG_IDX_WIDTH)
1163	) reg_0 (
1164	// ----- Inputs -------
1165	.read_clk (clk_n_i),
1166	.write_clk (clk_i),
1167	.reset (rst_i),
1168	.enable_read (stall_f == `FALSE),
1169	.read_address (read_idx_0_d),
1170	.enable_write (`TRUE),
1171	.write_address (write_idx_w),
1172	.write_data (w_result),
1173	.write_enable (reg_write_enable_q_w),
1174	// ----- Outputs -------
1175	.read_data (reg_data_0)
1176	);
1177
1178	lm32_ram #(
1179	// ----- Parameters -------
1180	.data_width (`LM32_WORD_WIDTH),
1181	.address_width (`LM32_REG_IDX_WIDTH)
1182	) reg_1 (
1183	// ----- Inputs -------
1184	.read_clk (clk_n_i),
1185	.write_clk (clk_i),
1186	.reset (rst_i),
1187	.enable_read (stall_f == `FALSE),
1188	.read_address (read_idx_1_d),
1189	.enable_write (`TRUE),
1190	.write_address (write_idx_w),
1191	.write_data (w_result),
1192	.write_enable (reg_write_enable_q_w),
1193	// ----- Outputs -------
1194	.read_data (reg_data_1)
1195	);
1196
1197	`endif
1198
1199
1200	/////////////////////////////////////////////////////
1201	// Combinational Logic
1202	/////////////////////////////////////////////////////
1203
1204	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
1205	// Select between buffered and live data from register file
1206	assign reg_data_0 = use_buf ? reg_data_buf_0 : reg_data_live_0;
1207	assign reg_data_1 = use_buf ? reg_data_buf_1 : reg_data_live_1;
1208	`endif
1209	`ifdef LM32_EBR_REGISTER_FILE
1210	`else
1211	// Register file read ports
1212	assign reg_data_0 = registers[read_idx_0_d];
1213	assign reg_data_1 = registers[read_idx_1_d];
1214	`endif
1215
1216	// Detect read-after-write hazzards
1217	assign raw_x_0 = (write_idx_x == read_idx_0_d) && (write_enable_q_x == `TRUE);
1218	assign raw_m_0 = (write_idx_m == read_idx_0_d) && (write_enable_q_m == `TRUE);
1219	assign raw_w_0 = (write_idx_w == read_idx_0_d) && (write_enable_q_w == `TRUE);
1220	assign raw_x_1 = (write_idx_x == read_idx_1_d) && (write_enable_q_x == `TRUE);
1221	assign raw_m_1 = (write_idx_m == read_idx_1_d) && (write_enable_q_m == `TRUE);
1222	assign raw_w_1 = (write_idx_w == read_idx_1_d) && (write_enable_q_w == `TRUE);
1223
1224	// Interlock detection - Raise an interlock for RAW hazzards
1225	always @*
1226	begin
1227	if ( ( (x_bypass_enable_x == `FALSE)
1228	&& ( ((read_enable_0_d == `TRUE) && (raw_x_0 == `TRUE))
1229	\|\| ((read_enable_1_d == `TRUE) && (raw_x_1 == `TRUE))
1230	)
1231	)
1232	\|\| ( (m_bypass_enable_m == `FALSE)
1233	&& ( ((read_enable_0_d == `TRUE) && (raw_m_0 == `TRUE))
1234	\|\| ((read_enable_1_d == `TRUE) && (raw_m_1 == `TRUE))
1235	)
1236	)
1237	)
1238	interlock = `TRUE;
1239	else
1240	interlock = `FALSE;
1241	end
1242
1243	// Bypass for reg port 0
1244	always @*
1245	begin
1246	if (raw_x_0 == `TRUE)
1247	bypass_data_0 = x_result;
1248	else if (raw_m_0 == `TRUE)
1249	bypass_data_0 = m_result;
1250	else if (raw_w_0 == `TRUE)
1251	bypass_data_0 = w_result;
1252	else
1253	bypass_data_0 = reg_data_0;
1254	end
1255
1256	// Bypass for reg port 1
1257	always @*
1258	begin
1259	if (raw_x_1 == `TRUE)
1260	bypass_data_1 = x_result;
1261	else if (raw_m_1 == `TRUE)
1262	bypass_data_1 = m_result;
1263	else if (raw_w_1 == `TRUE)
1264	bypass_data_1 = w_result;
1265	else
1266	bypass_data_1 = reg_data_1;
1267	end
1268
1269	// D stage result selection
1270	always @*
1271	begin
1272	d_result_0 = d_result_sel_0_d[0] ? {pc_f, 2'b00} : bypass_data_0;
1273	case (d_result_sel_1_d)
1274	`LM32_D_RESULT_SEL_1_ZERO: d_result_1 = {`LM32_WORD_WIDTH{1'b0}};
1275	`LM32_D_RESULT_SEL_1_REG_1: d_result_1 = bypass_data_1;
1276	`LM32_D_RESULT_SEL_1_IMMEDIATE: d_result_1 = immediate_d;
1277	default: d_result_1 = {`LM32_WORD_WIDTH{1'bx}};
1278	endcase
1279	end
1280
1281	`ifdef CFG_USER_ENABLED
1282	// Operands for user-defined instructions
1283	assign user_operand_0 = operand_0_x;
1284	assign user_operand_1 = operand_1_x;
1285	`endif
1286
1287	`ifdef CFG_SIGN_EXTEND_ENABLED
1288	// Sign-extension
1289	assign sextb_result_x = {{24{operand_0_x[7]}}, operand_0_x[7:0]};
1290	assign sexth_result_x = {{16{operand_0_x[15]}}, operand_0_x[15:0]};
1291	assign sext_result_x = size_x == `LM32_SIZE_BYTE ? sextb_result_x : sexth_result_x;
1292	`endif
1293
1294	`ifdef LM32_NO_BARREL_SHIFT
1295	// Only single bit shift operations are supported when barrel-shifter isn't implemented
1296	assign shifter_result_x = {operand_0_x[`LM32_WORD_WIDTH-1] & sign_extend_x, operand_0_x[`LM32_WORD_WIDTH-1:1]};
1297	`endif
1298
1299	// Condition evaluation
1300	assign cmp_zero = operand_0_x == operand_1_x;
1301	assign cmp_negative = adder_result_x[`LM32_WORD_WIDTH-1];
1302	assign cmp_overflow = adder_overflow_x;
1303	assign cmp_carry_n = adder_carry_n_x;
1304	always @*
1305	begin
1306	case (condition_x)
1307	`LM32_CONDITION_U1: condition_met_x = `TRUE;
1308	`LM32_CONDITION_U2: condition_met_x = `TRUE;
1309	`LM32_CONDITION_E: condition_met_x = cmp_zero;
1310	`LM32_CONDITION_NE: condition_met_x = !cmp_zero;
1311	`LM32_CONDITION_G: condition_met_x = !cmp_zero && (cmp_negative == cmp_overflow);
1312	`LM32_CONDITION_GU: condition_met_x = cmp_carry_n && !cmp_zero;
1313	`LM32_CONDITION_GE: condition_met_x = cmp_negative == cmp_overflow;
1314	`LM32_CONDITION_GEU: condition_met_x = cmp_carry_n;
1315	default: condition_met_x = 1'bx;
1316	endcase
1317	end
1318
1319	// X stage result selection
1320	always @*
1321	begin
1322	x_result = x_result_sel_add_x ? adder_result_x
1323	: x_result_sel_csr_x ? csr_read_data_x
1324	`ifdef CFG_SIGN_EXTEND_ENABLED
1325	: x_result_sel_sext_x ? sext_result_x
1326	`endif
1327	`ifdef CFG_USER_ENABLED
1328	: x_result_sel_user_x ? user_result
1329	`endif
1330	`ifdef LM32_NO_BARREL_SHIFT
1331	: x_result_sel_shift_x ? shifter_result_x
1332	`endif
1333	`ifdef LM32_MC_ARITHMETIC_ENABLED
1334	: x_result_sel_mc_arith_x ? mc_result_x
1335	`endif
1336	: logic_result_x;
1337	end
1338
1339	// M stage result selection
1340	always @*
1341	begin
1342	m_result = m_result_sel_compare_m ? {{`LM32_WORD_WIDTH-1{1'b0}}, condition_met_m}
1343	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1344	: m_result_sel_shift_m ? shifter_result_m
1345	`endif
1346	: operand_m;
1347	end
1348
1349	// W stage result selection
1350	always @*
1351	begin
1352	w_result = w_result_sel_load_w ? load_data_w
1353	`ifdef CFG_PL_MULTIPLY_ENABLED
1354	: w_result_sel_mul_w ? multiplier_result_w
1355	`endif
1356	: operand_w;
1357	end
1358
1359	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1360	// Indicate when a branch should be taken in X stage
1361	assign branch_taken_x = (stall_x == `FALSE)
1362	&& ( (branch_x == `TRUE)
1363	&& ((condition_x == `LM32_CONDITION_U1) \|\| (condition_x == `LM32_CONDITION_U2))
1364	&& (valid_x == `TRUE)
1365	);
1366	`endif
1367
1368	// Indicate when a branch should be taken in M stage (exceptions are a type of branch)
1369	assign branch_taken_m = (stall_m == `FALSE)
1370	&& ( ( (branch_m == `TRUE)
1371	&& (condition_met_m == `TRUE)
1372	&& (valid_m == `TRUE)
1373	)
1374	\|\| (exception_m == `TRUE)
1375	);
1376
1377	// Generate signal that will kill instructions in each pipeline stage when necessary
1378	assign kill_f = (branch_taken_m == `TRUE)
1379	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1380	\|\| (branch_taken_x == `TRUE)
1381	`endif
1382	`ifdef CFG_ICACHE_ENABLED
1383	\|\| (icache_refill_request == `TRUE)
1384	`endif
1385	`ifdef CFG_DCACHE_ENABLED
1386	\|\| (dcache_refill_request == `TRUE)
1387	`endif
1388	;
1389	assign kill_d = (branch_taken_m == `TRUE)
1390	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
1391	\|\| (branch_taken_x == `TRUE)
1392	`endif
1393	`ifdef CFG_ICACHE_ENABLED
1394	\|\| (icache_refill_request == `TRUE)
1395	`endif
1396	`ifdef CFG_DCACHE_ENABLED
1397	\|\| (dcache_refill_request == `TRUE)
1398	`endif
1399	;
1400	assign kill_x = (branch_taken_m == `TRUE)
1401	`ifdef CFG_DCACHE_ENABLED
1402	\|\| (dcache_refill_request == `TRUE)
1403	`endif
1404	;
1405	assign kill_m = `FALSE
1406	`ifdef CFG_DCACHE_ENABLED
1407	\|\| (dcache_refill_request == `TRUE)
1408	`endif
1409	;
1410	assign kill_w = `FALSE
1411	`ifdef CFG_DCACHE_ENABLED
1412	\|\| (dcache_refill_request == `TRUE)
1413	`endif
1414	;
1415
1416	// Exceptions
1417
1418	`ifdef CFG_DEBUG_ENABLED
1419	assign breakpoint_exception = (break_x == `TRUE)
1420	\|\| (bp_match == `TRUE)
1421	`ifdef CFG_JTAG_ENABLED
1422	\|\| (jtag_break == `TRUE)
1423	`endif
1424	;
1425	assign watchpoint_exception = wp_match == `TRUE;
1426	`endif
1427	`ifdef CFG_BUS_ERRORS_ENABLED
1428	assign instruction_bus_error_exception = bus_error_x == `TRUE;
1429	assign data_bus_error_exception = data_bus_error_seen == `TRUE;
1430	`endif
1431	`ifdef CFG_MC_DIVIDE_ENABLED
1432	assign divide_by_zero_exception = divide_by_zero_x == `TRUE;
1433	`endif
1434	assign system_call_exception = scall_x == `TRUE;
1435
1436	`ifdef CFG_DEBUG_ENABLED
1437	assign debug_exception_x = (breakpoint_exception == `TRUE)
1438	\|\| (watchpoint_exception == `TRUE)
1439	;
1440
1441	assign non_debug_exception_x = (system_call_exception == `TRUE)
1442	`ifdef CFG_JTAG_ENABLED
1443	\|\| (reset_exception == `TRUE)
1444	`endif
1445	`ifdef CFG_BUS_ERRORS_ENABLED
1446	\|\| (instruction_bus_error_exception == `TRUE)
1447	\|\| (data_bus_error_exception == `TRUE)
1448	`endif
1449	`ifdef CFG_MC_DIVIDE_ENABLED
1450	\|\| (divide_by_zero_exception == `TRUE)
1451	`endif
1452	`ifdef CFG_INTERRUPTS_ENABLED
1453	\|\| ( (interrupt_exception == `TRUE)
1454	`ifdef LM32_SINGLE_STEP_ENABLED
1455	&& (dc_ss == `FALSE)
1456	`endif
1457	)
1458	`endif
1459	;
1460
1461	assign exception_x = (debug_exception_x == `TRUE) \|\| (non_debug_exception_x == `TRUE);
1462	`else
1463	assign exception_x = (system_call_exception == `TRUE)
1464	`ifdef CFG_BUS_ERRORS_ENABLED
1465	\|\| (instruction_bus_error_exception == `TRUE)
1466	\|\| (data_bus_error_exception == `TRUE)
1467	`endif
1468	`ifdef CFG_MC_DIVIDE_ENABLED
1469	\|\| (divide_by_zero_exception == `TRUE)
1470	`endif
1471	`ifdef CFG_INTERRUPTS_ENABLED
1472	\|\| ( (interrupt_exception == `TRUE)
1473	`ifdef LM32_SINGLE_STEP_ENABLED
1474	&& (dc_ss == `FALSE)
1475	`endif
1476	)
1477	`endif
1478	;
1479	`endif
1480
1481	// Exception ID
1482	always @*
1483	begin
1484	`ifdef CFG_DEBUG_ENABLED
1485	`ifdef CFG_JTAG_ENABLED
1486	if (reset_exception == `TRUE)
1487	eid_x = `LM32_EID_RESET;
1488	else
1489	`endif
1490	if (breakpoint_exception == `TRUE)
1491	eid_x = `LM32_EID_BREAKPOINT;
1492	else
1493	`endif
1494	`ifdef CFG_BUS_ERRORS_ENABLED
1495	if (instruction_bus_error_exception == `TRUE)
1496	eid_x = `LM32_EID_INST_BUS_ERROR;
1497	else
1498	`endif
1499	`ifdef CFG_DEBUG_ENABLED
1500	if (watchpoint_exception == `TRUE)
1501	eid_x = `LM32_EID_WATCHPOINT;
1502	else
1503	`endif
1504	`ifdef CFG_BUS_ERRORS_ENABLED
1505	if (data_bus_error_exception == `TRUE)
1506	eid_x = `LM32_EID_DATA_BUS_ERROR;
1507	else
1508	`endif
1509	`ifdef CFG_MC_DIVIDE_ENABLED
1510	if (divide_by_zero_exception == `TRUE)
1511	eid_x = `LM32_EID_DIVIDE_BY_ZERO;
1512	else
1513	`endif
1514	`ifdef CFG_INTERRUPTS_ENABLED
1515	if ( (interrupt_exception == `TRUE)
1516	`ifdef LM32_SINGLE_STEP_ENABLED
1517	&& (dc_ss == `FALSE)
1518	`endif
1519	)
1520	eid_x = `LM32_EID_INTERRUPT;
1521	else
1522	`endif
1523	eid_x = `LM32_EID_SCALL;
1524	end
1525
1526	// Stall generation
1527
1528	assign stall_a = (stall_f == `TRUE);
1529
1530	assign stall_f = (stall_d == `TRUE);
1531
1532	assign stall_d = (stall_x == `TRUE)
1533	\|\| ( (interlock == `TRUE)
1534	&& (kill_d == `FALSE)
1535	)
1536	\|\| ( (eret_d == `TRUE)
1537	&& (load_q_x == `TRUE)
1538	)
1539	`ifdef CFG_DEBUG_ENABLED
1540	\|\| ( (bret_d == `TRUE)
1541	&& (load_q_x == `TRUE)
1542	)
1543	`endif
1544	\|\| ( (csr_write_enable_d == `TRUE)
1545	&& (load_q_x == `TRUE)
1546	)
1547	;
1548
1549	assign stall_x = (stall_m == `TRUE)
1550	`ifdef LM32_MC_ARITHMETIC_ENABLED
1551	\|\| ( (mc_stall_request_x == `TRUE)
1552	&& (kill_x == `FALSE)
1553	)
1554	`endif
1555	;
1556
1557	assign stall_m = (stall_wb_load == `TRUE)
1558	`ifdef CFG_SIZE_OVER_SPEED
1559	\|\| (D_CYC_O == `TRUE)
1560	`else
1561	\|\| ( (D_CYC_O == `TRUE)
1562	&& ( (store_m == `TRUE)
1563	\|\| (load_m == `TRUE)
1564	\|\| (load_x == `TRUE)
1565	)
1566	)
1567	`endif
1568	`ifdef CFG_DCACHE_ENABLED
1569	\|\| (dcache_stall_request == `TRUE) // Need to stall in case a taken branch is in M stage and data cache is only being flush, so wont be restarted
1570	`endif
1571	`ifdef CFG_ICACHE_ENABLED
1572	\|\| (icache_stall_request == `TRUE) // Pipeline needs to be stalled otherwise branches may be lost
1573	\|\| ((I_CYC_O == `TRUE) && ((branch_m == `TRUE) \|\| (exception_m == `TRUE)))
1574	`else
1575	`ifdef CFG_IWB_ENABLED
1576	\|\| (I_CYC_O == `TRUE)
1577	`endif
1578	`endif
1579	`ifdef CFG_USER_ENABLED
1580	\|\| ( (user_valid == `TRUE) // Stall whole pipeline, rather than just X stage, where the instruction is, so we don't have to worry about exceptions (maybe)
1581	&& (user_complete == `FALSE)
1582	)
1583	`endif
1584	;
1585
1586	// Qualify state changing control signals
1587	`ifdef LM32_MC_ARITHMETIC_ENABLED
1588	wire q_d = (valid_d == `TRUE) && (kill_d == `FALSE);
1589	`endif
1590	`ifdef CFG_MC_BARREL_SHIFT_ENABLED
1591	assign shift_left_q_d = (shift_left_d == `TRUE) && (q_d == `TRUE);
1592	assign shift_right_q_d = (shift_right_d == `TRUE) && (q_d == `TRUE);
1593	`endif
1594	`ifdef CFG_MC_MULTIPLY_ENABLED
1595	assign multiply_q_d = (multiply_d == `TRUE) && (q_d == `TRUE);
1596	`endif
1597	`ifdef CFG_MC_DIVIDE_ENABLED
1598	assign divide_q_d = (divide_d == `TRUE) && (q_d == `TRUE);
1599	assign modulus_q_d = (modulus_d == `TRUE) && (q_d == `TRUE);
1600	`endif
1601	wire q_x = (valid_x == `TRUE) && (kill_x == `FALSE);
1602	assign csr_write_enable_q_x = (csr_write_enable_x == `TRUE) && (q_x == `TRUE);
1603	assign eret_q_x = (eret_x == `TRUE) && (q_x == `TRUE);
1604	`ifdef CFG_DEBUG_ENABLED
1605	assign bret_q_x = (bret_x == `TRUE) && (q_x == `TRUE);
1606	`endif
1607	assign load_q_x = (load_x == `TRUE)
1608	&& (q_x == `TRUE)
1609	`ifdef CFG_DEBUG_ENABLED
1610	&& (bp_match == `FALSE)
1611	`endif
1612	;
1613	`ifdef CFG_USER_ENABLED
1614	assign user_valid = (x_result_sel_user_x == `TRUE) && (q_x == `TRUE);
1615	`endif
1616	wire q_m = (valid_m == `TRUE) && (kill_m == `FALSE) && (exception_m == `FALSE);
1617	assign load_q_m = (load_m == `TRUE) && (q_m == `TRUE);
1618	assign store_q_m = (store_m == `TRUE) && (q_m == `TRUE);
1619	`ifdef CFG_DEBUG_ENABLED
1620	assign debug_exception_q_w = ((debug_exception_w == `TRUE) && (valid_w == `TRUE));
1621	assign non_debug_exception_q_w = ((non_debug_exception_w == `TRUE) && (valid_w == `TRUE));
1622	`else
1623	assign exception_q_w = ((exception_w == `TRUE) && (valid_w == `TRUE));
1624	`endif
1625	// Don't qualify register write enables with kill, as the signal is needed early, and it doesn't matter if the instruction is killed (except for the actual write - but that is handled separately)
1626	assign write_enable_q_x = (write_enable_x == `TRUE) && (valid_x == `TRUE);
1627	assign write_enable_q_m = (write_enable_m == `TRUE) && (valid_m == `TRUE);
1628	assign write_enable_q_w = (write_enable_w == `TRUE) && (valid_w == `TRUE);
1629	// The enable that actually does write the registers needs to be qualified with kill
1630	assign reg_write_enable_q_w = (write_enable_w == `TRUE) && (kill_w == `FALSE) && (valid_w == `TRUE);
1631
1632	// Configuration (CFG) CSR
1633	assign cfg = {
1634	`LM32_REVISION,
1635	watchpoints[3:0],
1636	breakpoints[3:0],
1637	interrupts[5:0],
1638	`ifdef CFG_JTAG_UART_ENABLED
1639	`TRUE,
1640	`else
1641	`FALSE,
1642	`endif
1643	`ifdef CFG_ROM_DEBUG_ENABLED
1644	`TRUE,
1645	`else
1646	`FALSE,
1647	`endif
1648	`ifdef CFG_HW_DEBUG_ENABLED
1649	`TRUE,
1650	`else
1651	`FALSE,
1652	`endif
1653	`ifdef CFG_DEBUG_ENABLED
1654	`TRUE,
1655	`else
1656	`FALSE,
1657	`endif
1658	`ifdef CFG_ICACHE_ENABLED
1659	`TRUE,
1660	`else
1661	`FALSE,
1662	`endif
1663	`ifdef CFG_DCACHE_ENABLED
1664	`TRUE,
1665	`else
1666	`FALSE,
1667	`endif
1668	`ifdef CFG_CYCLE_COUNTER_ENABLED
1669	`TRUE,
1670	`else
1671	`FALSE,
1672	`endif
1673	`ifdef CFG_USER_ENABLED
1674	`TRUE,
1675	`else
1676	`FALSE,
1677	`endif
1678	`ifdef CFG_SIGN_EXTEND_ENABLED
1679	`TRUE,
1680	`else
1681	`FALSE,
1682	`endif
1683	`ifdef LM32_BARREL_SHIFT_ENABLED
1684	`TRUE,
1685	`else
1686	`FALSE,
1687	`endif
1688	`ifdef CFG_MC_DIVIDE_ENABLED
1689	`TRUE,
1690	`else
1691	`FALSE,
1692	`endif
1693	`ifdef LM32_MULTIPLY_ENABLED
1694	`TRUE
1695	`else
1696	`FALSE
1697	`endif
1698	};
1699
1700	// Cache flush
1701	`ifdef CFG_ICACHE_ENABLED
1702	assign iflush = (csr_write_enable_d == `TRUE)
1703	&& (csr_d == `LM32_CSR_ICC)
1704	&& (stall_d == `FALSE)
1705	&& (kill_d == `FALSE)
1706	&& (valid_d == `TRUE);
1707	`endif
1708	`ifdef CFG_DCACHE_ENABLED
1709	assign dflush_x = (csr_write_enable_q_x == `TRUE)
1710	&& (csr_x == `LM32_CSR_DCC);
1711	`endif
1712
1713	// Extract CSR index
1714	assign csr_d = read_idx_0_d[`LM32_CSR_RNG];
1715
1716	// CSR reads
1717	always @*
1718	begin
1719	case (csr_x)
1720	`ifdef CFG_INTERRUPTS_ENABLED
1721	`LM32_CSR_IE,
1722	`LM32_CSR_IM,
1723	`LM32_CSR_IP: csr_read_data_x = interrupt_csr_read_data_x;
1724	`endif
1725	`ifdef CFG_CYCLE_COUNTER_ENABLED
1726	`LM32_CSR_CC: csr_read_data_x = cc;
1727	`endif
1728	`LM32_CSR_CFG: csr_read_data_x = cfg;
1729	`LM32_CSR_EBA: csr_read_data_x = {eba, 8'h00};
1730	`ifdef CFG_DEBUG_ENABLED
1731	`LM32_CSR_DEBA: csr_read_data_x = {deba, 8'h00};
1732	`endif
1733	`ifdef CFG_JTAG_UART_ENABLED
1734	`LM32_CSR_JTX: csr_read_data_x = jtx_csr_read_data;
1735	`LM32_CSR_JRX: csr_read_data_x = jrx_csr_read_data;
1736	`endif
1737	default: csr_read_data_x = {`LM32_WORD_WIDTH{1'bx}};
1738	endcase
1739	end
1740
1741	/////////////////////////////////////////////////////
1742	// Sequential Logic
1743	/////////////////////////////////////////////////////
1744
1745	// Exception Base Address (EBA) CSR
1746	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1747	begin
1748	if (rst_i == `TRUE)
1749	eba <= eba_reset[`LM32_PC_WIDTH+2-1:8];
1750	else
1751	begin
1752	if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_EBA) && (stall_x == `FALSE))
1753	eba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1754	`ifdef CFG_HW_DEBUG_ENABLED
1755	if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_EBA))
1756	eba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1757	`endif
1758	end
1759	end
1760
1761	`ifdef CFG_DEBUG_ENABLED
1762	// Debug Exception Base Address (DEBA) CSR
1763	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1764	begin
1765	if (rst_i == `TRUE)
1766	deba <= deba_reset[`LM32_PC_WIDTH+2-1:8];
1767	else
1768	begin
1769	if ((csr_write_enable_q_x == `TRUE) && (csr_x == `LM32_CSR_DEBA) && (stall_x == `FALSE))
1770	deba <= operand_1_x[`LM32_PC_WIDTH+2-1:8];
1771	`ifdef CFG_HW_DEBUG_ENABLED
1772	if ((jtag_csr_write_enable == `TRUE) && (jtag_csr == `LM32_CSR_DEBA))
1773	deba <= jtag_csr_write_data[`LM32_PC_WIDTH+2-1:8];
1774	`endif
1775	end
1776	end
1777	`endif
1778
1779	// Cycle Counter (CC) CSR
1780	`ifdef CFG_CYCLE_COUNTER_ENABLED
1781	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1782	begin
1783	if (rst_i == `TRUE)
1784	cc <= {`LM32_WORD_WIDTH{1'b0}};
1785	else
1786	cc <= cc + 1'b1;
1787	end
1788	`endif
1789
1790	`ifdef CFG_BUS_ERRORS_ENABLED
1791	// Watch for data bus errors
1792	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1793	begin
1794	if (rst_i == `TRUE)
1795	data_bus_error_seen <= `FALSE;
1796	else
1797	begin
1798	// Set flag when bus error is detected
1799	if ((D_ERR_I == `TRUE) && (D_CYC_O == `TRUE))
1800	data_bus_error_seen <= `TRUE;
1801	// Clear flag when exception is taken
1802	if ((exception_m == `TRUE) && (kill_m == `FALSE))
1803	data_bus_error_seen <= `FALSE;
1804	end
1805	end
1806	`endif
1807
1808	// Valid bits to indicate whether an instruction in a partcular pipeline stage is valid or not
1809
1810	`ifdef CFG_ICACHE_ENABLED
1811	`ifdef CFG_DCACHE_ENABLED
1812	always @*
1813	begin
1814	if ( (icache_refill_request == `TRUE)
1815	\|\| (dcache_refill_request == `TRUE)
1816	)
1817	valid_a = `FALSE;
1818	else if ( (icache_restart_request == `TRUE)
1819	\|\| (dcache_restart_request == `TRUE)
1820	)
1821	valid_a = `TRUE;
1822	else
1823	valid_a = !icache_refilling && !dcache_refilling;
1824	end
1825	`else
1826	always @*
1827	begin
1828	if (icache_refill_request == `TRUE)
1829	valid_a = `FALSE;
1830	else if (icache_restart_request == `TRUE)
1831	valid_a = `TRUE;
1832	else
1833	valid_a = !icache_refilling;
1834	end
1835	`endif
1836	`else
1837	`ifdef CFG_DCACHE_ENABLED
1838	always @*
1839	begin
1840	if (dcache_refill_request == `TRUE)
1841	valid_a = `FALSE;
1842	else if (dcache_restart_request == `TRUE)
1843	valid_a = `TRUE;
1844	else
1845	valid_a = !dcache_refilling;
1846	end
1847	`endif
1848	`endif
1849
1850	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1851	begin
1852	if (rst_i == `TRUE)
1853	begin
1854	valid_f <= `FALSE;
1855	valid_d <= `FALSE;
1856	valid_x <= `FALSE;
1857	valid_m <= `FALSE;
1858	valid_w <= `FALSE;
1859	end
1860	else
1861	begin
1862	if ((kill_f == `TRUE) \|\| (stall_a == `FALSE))
1863	`ifdef LM32_CACHE_ENABLED
1864	valid_f <= valid_a;
1865	`else
1866	valid_f <= `TRUE;
1867	`endif
1868	else if (stall_f == `FALSE)
1869	valid_f <= `FALSE;
1870	if (kill_d == `TRUE)
1871	valid_d <= `FALSE;
1872	else if (stall_f == `FALSE)
1873	valid_d <= valid_f & !kill_f;
1874	else if (stall_d == `FALSE)
1875	valid_d <= `FALSE;
1876	if (kill_x == `TRUE)
1877	valid_x <= `FALSE;
1878	else if (stall_d == `FALSE)
1879	valid_x <= valid_d & !kill_d;
1880	else if (stall_x == `FALSE)
1881	valid_x <= `FALSE;
1882	if (kill_m == `TRUE)
1883	valid_m <= `FALSE;
1884	else if (stall_x == `FALSE)
1885	valid_m <= valid_x & !kill_x;
1886	else if (stall_m == `FALSE)
1887	valid_m <= `FALSE;
1888	if (stall_m == `FALSE)
1889	valid_w <= valid_m & !kill_m;
1890	else
1891	valid_w <= `FALSE;
1892	end
1893	end
1894
1895	// Microcode pipeline registers
1896	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
1897	begin
1898	if (rst_i == `TRUE)
1899	begin
1900	`ifdef CFG_USER_ENABLED
1901	user_opcode <= {`LM32_USER_OPCODE_WIDTH{1'b0}};
1902	`endif
1903	operand_0_x <= {`LM32_WORD_WIDTH{1'b0}};
1904	operand_1_x <= {`LM32_WORD_WIDTH{1'b0}};
1905	store_operand_x <= {`LM32_WORD_WIDTH{1'b0}};
1906	branch_target_x <= {`LM32_WORD_WIDTH{1'b0}};
1907	x_result_sel_csr_x <= `FALSE;
1908	`ifdef LM32_MC_ARITHMETIC_ENABLED
1909	x_result_sel_mc_arith_x <= `FALSE;
1910	`endif
1911	`ifdef LM32_NO_BARREL_SHIFT
1912	x_result_sel_shift_x <= `FALSE;
1913	`endif
1914	`ifdef CFG_SIGN_EXTEND_ENABLED
1915	x_result_sel_sext_x <= `FALSE;
1916	`endif
1917	x_result_sel_logic_x <= `FALSE;
1918	`ifdef CFG_USER_ENABLED
1919	x_result_sel_user_x <= `FALSE;
1920	`endif
1921	x_result_sel_add_x <= `FALSE;
1922	m_result_sel_compare_x <= `FALSE;
1923	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1924	m_result_sel_shift_x <= `FALSE;
1925	`endif
1926	w_result_sel_load_x <= `FALSE;
1927	`ifdef CFG_PL_MULTIPLY_ENABLED
1928	w_result_sel_mul_x <= `FALSE;
1929	`endif
1930	x_bypass_enable_x <= `FALSE;
1931	m_bypass_enable_x <= `FALSE;
1932	write_enable_x <= `FALSE;
1933	write_idx_x <= {`LM32_REG_IDX_WIDTH{1'b0}};
1934	csr_x <= {`LM32_CSR_WIDTH{1'b0}};
1935	load_x <= `FALSE;
1936	store_x <= `FALSE;
1937	size_x <= {`LM32_SIZE_WIDTH{1'b0}};
1938	sign_extend_x <= `FALSE;
1939	adder_op_x <= `FALSE;
1940	adder_op_x_n <= `FALSE;
1941	logic_op_x <= 4'h0;
1942	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1943	direction_x <= `FALSE;
1944	`endif
1945	`ifdef CFG_ROTATE_ENABLED
1946	rotate_x <= `FALSE;
1947
1948	`endif
1949	branch_x <= `FALSE;
1950	condition_x <= `LM32_CONDITION_U1;
1951	`ifdef CFG_DEBUG_ENABLED
1952	break_x <= `FALSE;
1953	`endif
1954	scall_x <= `FALSE;
1955	eret_x <= `FALSE;
1956	`ifdef CFG_DEBUG_ENABLED
1957	bret_x <= `FALSE;
1958	`endif
1959	`ifdef CFG_BUS_ERRORS_ENABLED
1960	bus_error_x <= `FALSE;
1961	`endif
1962	csr_write_enable_x <= `FALSE;
1963	operand_m <= {`LM32_WORD_WIDTH{1'b0}};
1964	branch_target_m <= {`LM32_WORD_WIDTH{1'b0}};
1965	m_result_sel_compare_m <= `FALSE;
1966	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1967	m_result_sel_shift_m <= `FALSE;
1968	`endif
1969	w_result_sel_load_m <= `FALSE;
1970	`ifdef CFG_PL_MULTIPLY_ENABLED
1971	w_result_sel_mul_m <= `FALSE;
1972	`endif
1973	m_bypass_enable_m <= `FALSE;
1974	branch_m <= `FALSE;
1975	exception_m <= `FALSE;
1976	load_m <= `FALSE;
1977	store_m <= `FALSE;
1978	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
1979	direction_m <= `FALSE;
1980	`endif
1981	write_enable_m <= `FALSE;
1982	write_idx_m <= {`LM32_REG_IDX_WIDTH{1'b0}};
1983	condition_met_m <= `FALSE;
1984	`ifdef CFG_DCACHE_ENABLED
1985	dflush_m <= `FALSE;
1986	`endif
1987	`ifdef CFG_DEBUG_ENABLED
1988	debug_exception_m <= `FALSE;
1989	non_debug_exception_m <= `FALSE;
1990	`endif
1991	operand_w <= {`LM32_WORD_WIDTH{1'b0}};
1992	w_result_sel_load_w <= `FALSE;
1993	`ifdef CFG_PL_MULTIPLY_ENABLED
1994	w_result_sel_mul_w <= `FALSE;
1995	`endif
1996	write_idx_w <= {`LM32_REG_IDX_WIDTH{1'b0}};
1997	write_enable_w <= `FALSE;
1998	`ifdef CFG_DEBUG_ENABLED
1999	debug_exception_w <= `FALSE;
2000	non_debug_exception_w <= `FALSE;
2001	`else
2002	exception_w <= `FALSE;
2003	`endif
2004	end
2005	else
2006	begin
2007	// D/X stage registers
2008
2009	if (stall_x == `FALSE)
2010	begin
2011	`ifdef CFG_USER_ENABLED
2012	user_opcode <= user_opcode_d;
2013	`endif
2014	operand_0_x <= d_result_0;
2015	operand_1_x <= d_result_1;
2016	store_operand_x <= bypass_data_1;
2017	branch_target_x <= branch_reg_d == `TRUE ? bypass_data_0[`LM32_PC_RNG] : pc_d + branch_offset_d;
2018	x_result_sel_csr_x <= x_result_sel_csr_d;
2019	`ifdef LM32_MC_ARITHMETIC_ENABLED
2020	x_result_sel_mc_arith_x <= x_result_sel_mc_arith_d;
2021	`endif
2022	`ifdef LM32_NO_BARREL_SHIFT
2023	x_result_sel_shift_x <= x_result_sel_shift_d;
2024	`endif
2025	`ifdef CFG_SIGN_EXTEND_ENABLED
2026	x_result_sel_sext_x <= x_result_sel_sext_d;
2027	`endif
2028	x_result_sel_logic_x <= x_result_sel_logic_d;
2029	`ifdef CFG_USER_ENABLED
2030	x_result_sel_user_x <= x_result_sel_user_d;
2031	`endif
2032	x_result_sel_add_x <= x_result_sel_add_d;
2033	m_result_sel_compare_x <= m_result_sel_compare_d;
2034	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2035	m_result_sel_shift_x <= m_result_sel_shift_d;
2036	`endif
2037	w_result_sel_load_x <= w_result_sel_load_d;
2038	`ifdef CFG_PL_MULTIPLY_ENABLED
2039	w_result_sel_mul_x <= w_result_sel_mul_d;
2040	`endif
2041	x_bypass_enable_x <= x_bypass_enable_d;
2042	m_bypass_enable_x <= m_bypass_enable_d;
2043	load_x <= load_d;
2044	store_x <= store_d;
2045	branch_x <= branch_d;
2046	write_idx_x <= write_idx_d;
2047	csr_x <= csr_d;
2048	size_x <= size_d;
2049	sign_extend_x <= sign_extend_d;
2050	adder_op_x <= adder_op_d;
2051	adder_op_x_n <= ~adder_op_d;
2052	logic_op_x <= logic_op_d;
2053	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2054	direction_x <= direction_d;
2055	`endif
2056	`ifdef CFG_ROTATE_ENABLED
2057	rotate_x <= rotate_d;
2058	`endif
2059	condition_x <= condition_d;
2060	csr_write_enable_x <= csr_write_enable_d;
2061	`ifdef CFG_DEBUG_ENABLED
2062	break_x <= break_d;
2063	`endif
2064	scall_x <= scall_d;
2065	`ifdef CFG_BUS_ERRORS_ENABLED
2066	bus_error_x <= bus_error_d;
2067	`endif
2068	eret_x <= eret_d;
2069	`ifdef CFG_DEBUG_ENABLED
2070	bret_x <= bret_d;
2071	`endif
2072	write_enable_x <= write_enable_d;
2073	end
2074
2075	// X/M stage registers
2076
2077	if (stall_m == `FALSE)
2078	begin
2079	operand_m <= x_result;
2080	m_result_sel_compare_m <= m_result_sel_compare_x;
2081	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2082	m_result_sel_shift_m <= m_result_sel_shift_x;
2083	`endif
2084	if (exception_x == `TRUE)
2085	begin
2086	w_result_sel_load_m <= `FALSE;
2087	`ifdef CFG_PL_MULTIPLY_ENABLED
2088	w_result_sel_mul_m <= `FALSE;
2089	`endif
2090	end
2091	else
2092	begin
2093	w_result_sel_load_m <= w_result_sel_load_x;
2094	`ifdef CFG_PL_MULTIPLY_ENABLED
2095	w_result_sel_mul_m <= w_result_sel_mul_x;
2096	`endif
2097	end
2098	m_bypass_enable_m <= m_bypass_enable_x;
2099	`ifdef CFG_PL_BARREL_SHIFT_ENABLED
2100	direction_m <= direction_x;
2101	`endif
2102	load_m <= load_x;
2103	store_m <= store_x;
2104	`ifdef CFG_FAST_UNCONDITIONAL_BRANCH
2105	branch_m <= branch_x && !branch_taken_x;
2106	`else
2107	branch_m <= branch_x;
2108	`endif
2109	`ifdef CFG_DEBUG_ENABLED
2110	if (debug_exception_x == `TRUE)
2111	write_idx_m <= `LM32_BA_REG;
2112	else if (non_debug_exception_x == `TRUE)
2113	write_idx_m <= `LM32_EA_REG;
2114	else
2115	write_idx_m <= write_idx_x;
2116	`else
2117	if (exception_x == `TRUE)
2118	write_idx_m <= `LM32_EA_REG;
2119	else
2120	write_idx_m <= write_idx_x;
2121	`endif
2122	condition_met_m <= condition_met_x;
2123	`ifdef CFG_DEBUG_ENABLED
2124	branch_target_m <= exception_x == `TRUE ? {(debug_exception_x == `TRUE) \|\| (dc_re == `TRUE) ? deba : eba, eid_x, {3{1'b0}}} : branch_target_x;
2125	`else
2126	branch_target_m <= exception_x == `TRUE ? {eba, eid_x, {3{1'b0}}} : branch_target_x;
2127	`endif
2128	`ifdef CFG_TRACE_ENABLED
2129	eid_m <= eid_x;
2130	`endif
2131	`ifdef CFG_DCACHE_ENABLED
2132	dflush_m <= dflush_x;
2133	`endif
2134	eret_m <= eret_q_x;
2135	`ifdef CFG_DEBUG_ENABLED
2136	bret_m <= bret_q_x;
2137	`endif
2138	write_enable_m <= exception_x == `TRUE ? `TRUE : write_enable_x;
2139	`ifdef CFG_DEBUG_ENABLED
2140	debug_exception_m <= debug_exception_x;
2141	non_debug_exception_m <= non_debug_exception_x;
2142	`endif
2143	end
2144
2145	// State changing regs
2146	if (stall_m == `FALSE)
2147	begin
2148	if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
2149	exception_m <= `TRUE;
2150	else
2151	exception_m <= `FALSE;
2152	end
2153
2154	// M/W stage registers
2155
2156	operand_w <= exception_m == `TRUE ? {pc_m, 2'b00} : m_result;
2157	w_result_sel_load_w <= w_result_sel_load_m;
2158	`ifdef CFG_PL_MULTIPLY_ENABLED
2159	w_result_sel_mul_w <= w_result_sel_mul_m;
2160	`endif
2161	write_idx_w <= write_idx_m;
2162	`ifdef CFG_TRACE_ENABLED
2163	eid_w <= eid_m;
2164	eret_w <= eret_m;
2165	`ifdef CFG_DEBUG_ENABLED
2166	bret_w <= bret_m;
2167	`endif
2168	`endif
2169	write_enable_w <= write_enable_m;
2170	`ifdef CFG_DEBUG_ENABLED
2171	debug_exception_w <= debug_exception_m;
2172	non_debug_exception_w <= non_debug_exception_m;
2173	`else
2174	exception_w <= exception_m;
2175	`endif
2176	end
2177	end
2178
2179	`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
2180	// Buffer data read from register file, in case a stall occurs, and watch for
2181	// any writes to the modified registers
2182	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2183	begin
2184	if (rst_i == `TRUE)
2185	begin
2186	use_buf <= `FALSE;
2187	reg_data_buf_0 <= {`LM32_WORD_WIDTH{1'b0}};
2188	reg_data_buf_1 <= {`LM32_WORD_WIDTH{1'b0}};
2189	end
2190	else
2191	begin
2192	if (stall_d == `FALSE)
2193	use_buf <= `FALSE;
2194	else if (use_buf == `FALSE)
2195	begin
2196	reg_data_buf_0 <= reg_data_live_0;
2197	reg_data_buf_1 <= reg_data_live_1;
2198	use_buf <= `TRUE;
2199	end
2200	if (reg_write_enable_q_w == `TRUE)
2201	begin
2202	if (write_idx_w == read_idx_0_d)
2203	reg_data_buf_0 <= w_result;
2204	if (write_idx_w == read_idx_1_d)
2205	reg_data_buf_1 <= w_result;
2206	end
2207	end
2208	end
2209	`endif
2210
2211	`ifdef LM32_EBR_REGISTER_FILE
2212	`else
2213	// Register file write port
2214	// Adding a reset causes a huge slowdown and requires lots of extra LUTs
2215	always @(posedge clk_i)
2216	begin
2217	if (reg_write_enable_q_w == `TRUE)
2218	registers[write_idx_w] <= w_result;
2219	end
2220	`endif
2221
2222	`ifdef CFG_TRACE_ENABLED
2223	// PC tracing logic
2224	always @(posedge clk_i `CFG_RESET_SENSITIVITY)
2225	begin
2226	if (rst_i == `TRUE)
2227	begin
2228	trace_pc_valid <= `FALSE;
2229	trace_pc <= {`LM32_PC_WIDTH{1'b0}};
2230	trace_exception <= `FALSE;
2231	trace_eid <= `LM32_EID_RESET;
2232	trace_eret <= `FALSE;
2233	`ifdef CFG_DEBUG_ENABLED
2234	trace_bret <= `FALSE;
2235	`endif
2236	pc_c <= `CFG_EBA_RESET/4;
2237	end
2238	else
2239	begin
2240	trace_pc_valid <= `FALSE;
2241
2242	// Has an exception occured
2243	`ifdef CFG_DEBUG_ENABLED
2244	if ((debug_exception_q_w == `TRUE) \|\| (non_debug_exception_q_w == `TRUE))
2245	`else
2246	if (exception_q_w == `TRUE)
2247	`endif
2248	begin
2249	trace_exception <= `TRUE;
2250	trace_pc_valid <= `TRUE;
2251	trace_pc <= pc_w;
2252	trace_eid <= eid_w;
2253	end
2254	else
2255	trace_exception <= `FALSE;
2256
2257	if ((valid_w == `TRUE) && (!kill_w))
2258	begin
2259	// An instruction is commiting. Determine if it is non-sequential
2260	if (pc_c + 1'b1 != pc_w)
2261	begin
2262	// Non-sequential instruction
2263	trace_pc_valid <= `TRUE;
2264	trace_pc <= pc_w;
2265	end
2266	// Record PC so we can determine if next instruction is sequential or not
2267	pc_c <= pc_w;
2268	// Indicate if it was an eret/bret instruction
2269	trace_eret <= eret_w;
2270	`ifdef CFG_DEBUG_ENABLED
2271	trace_bret <= bret_w;
2272	`endif
2273	end
2274	else
2275	begin
2276	trace_eret <= `FALSE;
2277	`ifdef CFG_DEBUG_ENABLED
2278	trace_bret <= `FALSE;
2279	`endif
2280	end
2281	end
2282	end
2283	`endif
2284
2285	/////////////////////////////////////////////////////
2286	// Behavioural Logic
2287	/////////////////////////////////////////////////////
2288
2289	// synthesis translate_off
2290
2291	// Reset register 0. Only needed for simulation.
2292	initial
2293	begin
2294	`ifdef LM32_EBR_REGISTER_FILE
2295	reg_0.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2296	reg_1.mem[0] = {`LM32_WORD_WIDTH{1'b0}};
2297	`else
2298	registers[0] = {`LM32_WORD_WIDTH{1'b0}};
2299	`endif
2300	end
2301
2302	// synthesis translate_on
2303
2304	endmodule
2305

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