Root/lm32/logic/sakc/rtl/lm32/lm32_debug.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_debug.v
19// Title : Hardware debug registers and associated logic.
20// Dependencies : lm32_include.v
21// Version : 6.1.17
22// =============================================================================
23
24`include "lm32_include.v"
25
26`ifdef CFG_DEBUG_ENABLED
27
28// States for single-step FSM
29`define LM32_DEBUG_SS_STATE_RNG 2:0
30`define LM32_DEBUG_SS_STATE_IDLE 3'b000
31`define LM32_DEBUG_SS_STATE_WAIT_FOR_RET 3'b001
32`define LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN 3'b010
33`define LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT 3'b011
34`define LM32_DEBUG_SS_STATE_RESTART 3'b100
35
36/////////////////////////////////////////////////////
37// Module interface
38/////////////////////////////////////////////////////
39
40module lm32_debug (
41    // ----- Inputs -------
42    clk_i,
43    rst_i,
44    pc_x,
45    load_x,
46    store_x,
47    load_store_address_x,
48    csr_write_enable_x,
49    csr_write_data,
50    csr_x,
51`ifdef CFG_HW_DEBUG_ENABLED
52    jtag_csr_write_enable,
53    jtag_csr_write_data,
54    jtag_csr,
55`endif
56`ifdef LM32_SINGLE_STEP_ENABLED
57    eret_q_x,
58    bret_q_x,
59    stall_x,
60    exception_x,
61    q_x,
62`ifdef CFG_DCACHE_ENABLED
63    dcache_refill_request,
64`endif
65`endif
66    // ----- Outputs -------
67`ifdef LM32_SINGLE_STEP_ENABLED
68    dc_ss,
69`endif
70    dc_re,
71    bp_match,
72    wp_match
73    );
74    
75/////////////////////////////////////////////////////
76// Parameters
77/////////////////////////////////////////////////////
78
79parameter breakpoints = 0; // Number of breakpoint CSRs
80parameter watchpoints = 0; // Number of watchpoint CSRs
81
82/////////////////////////////////////////////////////
83// Inputs
84/////////////////////////////////////////////////////
85
86input clk_i; // Clock
87input rst_i; // Reset
88
89input [`LM32_PC_RNG] pc_x; // X stage PC
90input load_x; // Load instruction in X stage
91input store_x; // Store instruction in X stage
92input [`LM32_WORD_RNG] load_store_address_x; // Load or store effective address
93input csr_write_enable_x; // wcsr instruction in X stage
94input [`LM32_WORD_RNG] csr_write_data; // Data to write to CSR
95input [`LM32_CSR_RNG] csr_x; // Which CSR to write
96`ifdef CFG_HW_DEBUG_ENABLED
97input jtag_csr_write_enable; // JTAG interface CSR write enable
98input [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to CSR
99input [`LM32_CSR_RNG] jtag_csr; // Which CSR to write
100`endif
101`ifdef LM32_SINGLE_STEP_ENABLED
102input eret_q_x; // eret instruction in X stage
103input bret_q_x; // bret instruction in X stage
104input stall_x; // Instruction in X stage is stalled
105input exception_x; // An exception has occured in X stage
106input q_x; // Indicates the instruction in the X stage is qualified
107`ifdef CFG_DCACHE_ENABLED
108input dcache_refill_request; // Indicates data cache wants to be refilled
109`endif
110`endif
111
112/////////////////////////////////////////////////////
113// Outputs
114/////////////////////////////////////////////////////
115
116`ifdef LM32_SINGLE_STEP_ENABLED
117output dc_ss; // Single-step enable
118reg dc_ss;
119`endif
120output dc_re; // Remap exceptions
121reg dc_re;
122output bp_match; // Indicates a breakpoint has matched
123wire bp_match;
124output wp_match; // Indicates a watchpoint has matched
125wire wp_match;
126
127/////////////////////////////////////////////////////
128// Internal nets and registers
129/////////////////////////////////////////////////////
130
131genvar i; // Loop index for generate statements
132
133// Debug CSRs
134
135reg [`LM32_PC_RNG] bp_a[0:breakpoints-1]; // Instruction breakpoint address
136reg bp_e[0:breakpoints-1]; // Instruction breakpoint enable
137wire [0:breakpoints-1]bp_match_n; // Indicates if a h/w instruction breakpoint matched
138
139reg [`LM32_WPC_C_RNG] wpc_c[0:watchpoints-1]; // Watchpoint enable
140reg [`LM32_WORD_RNG] wp[0:watchpoints-1]; // Watchpoint address
141wire [0:watchpoints-1]wp_match_n; // Indicates if a h/w data watchpoint matched
142
143wire debug_csr_write_enable; // Debug CSR write enable (from either a wcsr instruction of external debugger)
144wire [`LM32_WORD_RNG] debug_csr_write_data; // Data to write to debug CSR
145wire [`LM32_CSR_RNG] debug_csr; // Debug CSR to write to
146
147`ifdef LM32_SINGLE_STEP_ENABLED
148// FIXME: Declaring this as a reg causes ModelSim 6.1.15b to crash, so use integer for now
149//reg [`LM32_DEBUG_SS_STATE_RNG] state; // State of single-step FSM
150integer state; // State of single-step FSM
151`endif
152
153/////////////////////////////////////////////////////
154// Functions
155/////////////////////////////////////////////////////
156
157`include "lm32_functions.v"
158
159/////////////////////////////////////////////////////
160// Combinational Logic
161/////////////////////////////////////////////////////
162
163// Check for breakpoints
164generate
165    for (i = 0; i < breakpoints; i = i + 1)
166    begin : bp_comb
167assign bp_match_n[i] = ((bp_a[i] == pc_x) && (bp_e[i] == `TRUE));
168    end
169endgenerate
170generate
171`ifdef LM32_SINGLE_STEP_ENABLED
172    if (breakpoints > 0)
173assign bp_match = (|bp_match_n) || (state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT);
174    else
175assign bp_match = state == `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
176`else
177    if (breakpoints > 0)
178assign bp_match = |bp_match_n;
179    else
180assign bp_match = `FALSE;
181`endif
182endgenerate
183               
184// Check for watchpoints
185generate
186    for (i = 0; i < watchpoints; i = i + 1)
187    begin : wp_comb
188assign wp_match_n[i] = (wp[i] == load_store_address_x) && ((load_x & wpc_c[i][0]) | (store_x & wpc_c[i][1]));
189    end
190endgenerate
191generate
192    if (watchpoints > 0)
193assign wp_match = |wp_match_n;
194    else
195assign wp_match = `FALSE;
196endgenerate
197                
198`ifdef CFG_HW_DEBUG_ENABLED
199// Multiplex between wcsr instruction writes and debugger writes to the debug CSRs
200assign debug_csr_write_enable = (csr_write_enable_x == `TRUE) || (jtag_csr_write_enable == `TRUE);
201assign debug_csr_write_data = jtag_csr_write_enable == `TRUE ? jtag_csr_write_data : csr_write_data;
202assign debug_csr = jtag_csr_write_enable == `TRUE ? jtag_csr : csr_x;
203`else
204assign debug_csr_write_enable = csr_write_enable_x;
205assign debug_csr_write_data = csr_write_data;
206assign debug_csr = csr_x;
207`endif
208
209/////////////////////////////////////////////////////
210// Sequential Logic
211/////////////////////////////////////////////////////
212
213// Breakpoint address and enable CSRs
214generate
215    for (i = 0; i < breakpoints; i = i + 1)
216    begin : bp_seq
217always @(posedge clk_i `CFG_RESET_SENSITIVITY)
218begin
219    if (rst_i == `TRUE)
220    begin
221        bp_a[i] <= {`LM32_PC_WIDTH{1'bx}};
222        bp_e[i] <= `FALSE;
223    end
224    else
225    begin
226        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_BP0 + i))
227        begin
228            bp_a[i] <= debug_csr_write_data[`LM32_PC_RNG];
229            bp_e[i] <= debug_csr_write_data[0];
230        end
231    end
232end
233    end
234endgenerate
235
236// Watchpoint address and control flags CSRs
237generate
238    for (i = 0; i < watchpoints; i = i + 1)
239    begin : wp_seq
240always @(posedge clk_i `CFG_RESET_SENSITIVITY)
241begin
242    if (rst_i == `TRUE)
243    begin
244        wp[i] <= {`LM32_WORD_WIDTH{1'bx}};
245        wpc_c[i] <= `LM32_WPC_C_DISABLED;
246    end
247    else
248    begin
249        if (debug_csr_write_enable == `TRUE)
250        begin
251            if (debug_csr == `LM32_CSR_DC)
252                wpc_c[i] <= debug_csr_write_data[3+i*2:2+i*2];
253            if (debug_csr == `LM32_CSR_WP0 + i)
254                wp[i] <= debug_csr_write_data;
255        end
256    end
257end
258    end
259endgenerate
260
261// Remap exceptions control bit
262always @(posedge clk_i `CFG_RESET_SENSITIVITY)
263begin
264    if (rst_i == `TRUE)
265        dc_re <= `FALSE;
266    else
267    begin
268        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
269            dc_re <= debug_csr_write_data[1];
270    end
271end
272
273`ifdef LM32_SINGLE_STEP_ENABLED
274// Single-step control flag
275always @(posedge clk_i `CFG_RESET_SENSITIVITY)
276begin
277    if (rst_i == `TRUE)
278    begin
279        state <= `LM32_DEBUG_SS_STATE_IDLE;
280        dc_ss <= `FALSE;
281    end
282    else
283    begin
284        if ((debug_csr_write_enable == `TRUE) && (debug_csr == `LM32_CSR_DC))
285        begin
286            dc_ss <= debug_csr_write_data[0];
287            if (debug_csr_write_data[0] == `FALSE)
288                state <= `LM32_DEBUG_SS_STATE_IDLE;
289            else
290                state <= `LM32_DEBUG_SS_STATE_WAIT_FOR_RET;
291        end
292        case (state)
293        `LM32_DEBUG_SS_STATE_WAIT_FOR_RET:
294        begin
295            // Wait for eret or bret instruction to be executed
296            if ( ( (eret_q_x == `TRUE)
297                    || (bret_q_x == `TRUE)
298                    )
299                && (stall_x == `FALSE)
300               )
301                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
302        end
303        `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN:
304        begin
305            // Wait for an instruction to be executed
306            if ((q_x == `TRUE) && (stall_x == `FALSE))
307                state <= `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT;
308        end
309        `LM32_DEBUG_SS_STATE_RAISE_BREAKPOINT:
310        begin
311            // Wait for exception to be raised
312`ifdef CFG_DCACHE_ENABLED
313            if (dcache_refill_request == `TRUE)
314                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
315            else
316`endif
317                 if ((exception_x == `TRUE) && (q_x == `TRUE) && (stall_x == `FALSE))
318            begin
319                dc_ss <= `FALSE;
320                state <= `LM32_DEBUG_SS_STATE_RESTART;
321            end
322        end
323        `LM32_DEBUG_SS_STATE_RESTART:
324        begin
325            // Watch to see if stepped instruction is restarted due to a cache miss
326`ifdef CFG_DCACHE_ENABLED
327            if (dcache_refill_request == `TRUE)
328                state <= `LM32_DEBUG_SS_STATE_EXECUTE_ONE_INSN;
329            else
330`endif
331                state <= `LM32_DEBUG_SS_STATE_IDLE;
332        end
333        endcase
334    end
335end
336`endif
337
338endmodule
339
340`endif
341

Archive Download this file

Branches:
master



interactive