Root/lm32/logic/sakc/rtl/lm32/lm32_include_all.v

1`ifndef LM32_ALL_FILES
2`define LM32_ALL_FILES
3//`ifndef SIMULATION
4//`include "pmi_def.v"
5//`endif
6// JTAG Debug related files
7`include "../components/lm32_top/rtl/verilog/er1.v"
8`include "../components/lm32_top/rtl/verilog/typeb.v"
9`include "../components/lm32_top/rtl/verilog/typea.v"
10`include "../components/lm32_top/rtl/verilog/jtag_cores.v"
11`include "../components/lm32_top/rtl/verilog/jtag_lm32.v"
12// CPU Core related files
13`include "../components/lm32_top/rtl/verilog/lm32_addsub.v"
14`include "../components/lm32_top/rtl/verilog/lm32_adder.v"
15`include "../components/lm32_top/rtl/verilog/lm32_cpu.v"
16`include "../components/lm32_top/rtl/verilog/lm32_dcache.v"
17`include "../components/lm32_top/rtl/verilog/lm32_debug.v"
18`include "../components/lm32_top/rtl/verilog/lm32_decoder.v"
19`include "../components/lm32_top/rtl/verilog/lm32_icache.v"
20`include "../components/lm32_top/rtl/verilog/lm32_instruction_unit.v"
21`include "../components/lm32_top/rtl/verilog/lm32_interrupt.v"
22`include "../components/lm32_top/rtl/verilog/lm32_load_store_unit.v"
23`include "../components/lm32_top/rtl/verilog/lm32_logic_op.v"
24`include "../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v"
25`include "../components/lm32_top/rtl/verilog/lm32_multiplier.v"
26`include "../components/lm32_top/rtl/verilog/lm32_shifter.v"
27`include "../components/lm32_top/rtl/verilog/lm32_top.v"
28`include "../components/lm32_top/rtl/verilog/lm32_monitor.v"
29`include "../components/lm32_top/rtl/verilog/lm32_monitor_ram.v"
30`include "../components/lm32_top/rtl/verilog/lm32_ram.v"
31`include "../components/lm32_top/rtl/verilog/lm32_jtag.v"
32`endif // LM32_ALL_FILES
33

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