Root/lm32/logic/sakc/rtl/lm32/lm32_jtag.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_jtag.v
19// Title : JTAG interface
20// Dependencies : lm32_include.v
21// Version : 6.1.17
22// =============================================================================
23
24`include "lm32_include.v"
25
26`ifdef CFG_JTAG_ENABLED
27
28`define LM32_DP 3'b000
29`define LM32_TX 3'b001
30`define LM32_RX 3'b010
31
32// LM32 Debug Protocol commands IDs
33`define LM32_DP_RNG 3:0
34`define LM32_DP_READ_MEMORY 4'b0001
35`define LM32_DP_WRITE_MEMORY 4'b0010
36`define LM32_DP_READ_SEQUENTIAL 4'b0011
37`define LM32_DP_WRITE_SEQUENTIAL 4'b0100
38`define LM32_DP_WRITE_CSR 4'b0101
39`define LM32_DP_BREAK 4'b0110
40`define LM32_DP_RESET 4'b0111
41
42// States for FSM
43`define LM32_JTAG_STATE_RNG 3:0
44`define LM32_JTAG_STATE_READ_COMMAND 4'h0
45`define LM32_JTAG_STATE_READ_BYTE_0 4'h1
46`define LM32_JTAG_STATE_READ_BYTE_1 4'h2
47`define LM32_JTAG_STATE_READ_BYTE_2 4'h3
48`define LM32_JTAG_STATE_READ_BYTE_3 4'h4
49`define LM32_JTAG_STATE_READ_BYTE_4 4'h5
50`define LM32_JTAG_STATE_PROCESS_COMMAND 4'h6
51`define LM32_JTAG_STATE_WAIT_FOR_MEMORY 4'h7
52`define LM32_JTAG_STATE_WAIT_FOR_CSR 4'h8
53
54/////////////////////////////////////////////////////
55// Module interface
56/////////////////////////////////////////////////////
57
58module lm32_jtag (
59    // ----- Inputs -------
60    clk_i,
61    rst_i,
62    jtag_clk,
63    jtag_update,
64    jtag_reg_q,
65    jtag_reg_addr_q,
66`ifdef CFG_JTAG_UART_ENABLED
67    csr,
68    csr_write_enable,
69    csr_write_data,
70    stall_x,
71`endif
72`ifdef CFG_HW_DEBUG_ENABLED
73    jtag_read_data,
74    jtag_access_complete,
75`endif
76`ifdef CFG_DEBUG_ENABLED
77    exception_q_w,
78`endif
79    // ----- Outputs -------
80`ifdef CFG_JTAG_UART_ENABLED
81    jtx_csr_read_data,
82    jrx_csr_read_data,
83`endif
84`ifdef CFG_HW_DEBUG_ENABLED
85    jtag_csr_write_enable,
86    jtag_csr_write_data,
87    jtag_csr,
88    jtag_read_enable,
89    jtag_write_enable,
90    jtag_write_data,
91    jtag_address,
92`endif
93`ifdef CFG_DEBUG_ENABLED
94    jtag_break,
95    jtag_reset,
96`endif
97    jtag_reg_d,
98    jtag_reg_addr_d
99    );
100
101   parameter lat_family = `LATTICE_FAMILY;
102   
103/////////////////////////////////////////////////////
104// Inputs
105/////////////////////////////////////////////////////
106
107input clk_i; // Clock
108input rst_i; // Reset
109
110input jtag_clk; // JTAG clock
111input jtag_update; // JTAG data register has been updated
112input [`LM32_BYTE_RNG] jtag_reg_q; // JTAG data register
113input [2:0] jtag_reg_addr_q; // JTAG data register
114
115`ifdef CFG_JTAG_UART_ENABLED
116input [`LM32_CSR_RNG] csr; // CSR to write
117input csr_write_enable; // CSR write enable
118input [`LM32_WORD_RNG] csr_write_data; // Data to write to specified CSR
119input stall_x; // Stall instruction in X stage
120`endif
121`ifdef CFG_HW_DEBUG_ENABLED
122input [`LM32_BYTE_RNG] jtag_read_data; // Data read from requested address
123input jtag_access_complete; // Memory access if complete
124`endif
125`ifdef CFG_DEBUG_ENABLED
126input exception_q_w; // Indicates an exception has occured in W stage
127`endif
128
129/////////////////////////////////////////////////////
130// Outputs
131/////////////////////////////////////////////////////
132       
133`ifdef CFG_JTAG_UART_ENABLED
134output [`LM32_WORD_RNG] jtx_csr_read_data; // Value of JTX CSR for rcsr instructions
135wire [`LM32_WORD_RNG] jtx_csr_read_data;
136output [`LM32_WORD_RNG] jrx_csr_read_data; // Value of JRX CSR for rcsr instructions
137wire [`LM32_WORD_RNG] jrx_csr_read_data;
138`endif
139`ifdef CFG_HW_DEBUG_ENABLED
140output jtag_csr_write_enable; // CSR write enable
141reg jtag_csr_write_enable;
142output [`LM32_WORD_RNG] jtag_csr_write_data; // Data to write to specified CSR
143wire [`LM32_WORD_RNG] jtag_csr_write_data;
144output [`LM32_CSR_RNG] jtag_csr; // CSR to write
145wire [`LM32_CSR_RNG] jtag_csr;
146output jtag_read_enable; // Memory read enable
147reg jtag_read_enable;
148output jtag_write_enable; // Memory write enable
149reg jtag_write_enable;
150output [`LM32_BYTE_RNG] jtag_write_data; // Data to write to specified address
151wire [`LM32_BYTE_RNG] jtag_write_data;
152output [`LM32_WORD_RNG] jtag_address; // Memory read/write address
153wire [`LM32_WORD_RNG] jtag_address;
154`endif
155`ifdef CFG_DEBUG_ENABLED
156output jtag_break; // Request to raise a breakpoint exception
157reg jtag_break;
158output jtag_reset; // Request to raise a reset exception
159reg jtag_reset;
160`endif
161output [`LM32_BYTE_RNG] jtag_reg_d;
162reg [`LM32_BYTE_RNG] jtag_reg_d;
163output [2:0] jtag_reg_addr_d;
164wire [2:0] jtag_reg_addr_d;
165             
166/////////////////////////////////////////////////////
167// Internal nets and registers
168/////////////////////////////////////////////////////
169
170reg rx_toggle; // Clock-domain crossing registers
171reg rx_toggle_r; // Registered version of rx_toggle
172reg rx_toggle_r_r; // Registered version of rx_toggle_r
173reg rx_toggle_r_r_r; // Registered version of rx_toggle_r_r
174
175reg [`LM32_BYTE_RNG] rx_byte;
176reg [2:0] rx_addr;
177
178`ifdef CFG_JTAG_UART_ENABLED
179reg [`LM32_BYTE_RNG] uart_tx_byte; // UART TX data
180reg uart_tx_valid; // TX data is valid
181reg [`LM32_BYTE_RNG] uart_rx_byte; // UART RX data
182reg uart_rx_valid; // RX data is valid
183`endif
184
185reg [`LM32_DP_RNG] command; // The last received command
186`ifdef CFG_HW_DEBUG_ENABLED
187reg [`LM32_BYTE_RNG] jtag_byte_0; // Registers to hold command paramaters
188reg [`LM32_BYTE_RNG] jtag_byte_1;
189reg [`LM32_BYTE_RNG] jtag_byte_2;
190reg [`LM32_BYTE_RNG] jtag_byte_3;
191reg [`LM32_BYTE_RNG] jtag_byte_4;
192reg processing; // Indicates if we're still processing a memory read/write
193`endif
194
195reg [`LM32_JTAG_STATE_RNG] state; // Current state of FSM
196
197/////////////////////////////////////////////////////
198// Combinational Logic
199/////////////////////////////////////////////////////
200
201`ifdef CFG_HW_DEBUG_ENABLED
202assign jtag_csr_write_data = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
203assign jtag_csr = jtag_byte_4[`LM32_CSR_RNG];
204assign jtag_address = {jtag_byte_0, jtag_byte_1, jtag_byte_2, jtag_byte_3};
205assign jtag_write_data = jtag_byte_4;
206`endif
207                 
208// Generate status flags for reading via the JTAG interface
209`ifdef CFG_JTAG_UART_ENABLED
210assign jtag_reg_addr_d[1:0] = {uart_rx_valid, uart_tx_valid};
211`else
212assign jtag_reg_addr_d[1:0] = 2'b00;
213`endif
214`ifdef CFG_HW_DEBUG_ENABLED
215assign jtag_reg_addr_d[2] = processing;
216`else
217assign jtag_reg_addr_d[2] = 1'b0;
218`endif
219
220`ifdef CFG_JTAG_UART_ENABLED
221assign jtx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_tx_valid, 8'h00};
222assign jrx_csr_read_data = {{`LM32_WORD_WIDTH-9{1'b0}}, uart_rx_valid, uart_rx_byte};
223`endif
224                 
225/////////////////////////////////////////////////////
226// Sequential Logic
227/////////////////////////////////////////////////////
228
229// Toggle a flag when a JTAG write occurs
230generate
231      if (lat_family == "EC" || lat_family == "ECP" ||
232      lat_family == "XP" || lat_family == "ECP2" || lat_family == "ECP2M") begin
233
234     always @(posedge jtag_clk `CFG_RESET_SENSITIVITY)
235       begin
236          if (rst_i == `TRUE)
237        rx_toggle <= 1'b0;
238          else
239        if (jtag_update == `TRUE)
240          rx_toggle <= ~rx_toggle;
241       end
242   
243      end else begin // for SC & SCM
244
245     always @(negedge jtag_update `CFG_RESET_SENSITIVITY)
246       begin
247          if (rst_i == `TRUE)
248        rx_toggle <= 1'b0;
249          else
250        rx_toggle <= ~rx_toggle;
251       end
252     
253      end
254endgenerate
255
256always @(*)
257begin
258    rx_byte = jtag_reg_q;
259    rx_addr = jtag_reg_addr_q;
260end
261
262// Clock domain crossing from JTAG clock domain to CPU clock domain
263always @(posedge clk_i `CFG_RESET_SENSITIVITY)
264begin
265    if (rst_i == `TRUE)
266    begin
267        rx_toggle_r <= 1'b0;
268        rx_toggle_r_r <= 1'b0;
269        rx_toggle_r_r_r <= 1'b0;
270    end
271    else
272    begin
273        rx_toggle_r <= rx_toggle;
274        rx_toggle_r_r <= rx_toggle_r;
275        rx_toggle_r_r_r <= rx_toggle_r_r;
276    end
277end
278
279// LM32 debug protocol state machine
280always @(posedge clk_i `CFG_RESET_SENSITIVITY)
281begin
282    if (rst_i == `TRUE)
283    begin
284        state <= `LM32_JTAG_STATE_READ_COMMAND;
285        command <= 4'b0000;
286        jtag_reg_d <= 8'h00;
287`ifdef CFG_HW_DEBUG_ENABLED
288        processing <= `FALSE;
289        jtag_csr_write_enable <= `FALSE;
290        jtag_read_enable <= `FALSE;
291        jtag_write_enable <= `FALSE;
292`endif
293`ifdef CFG_DEBUG_ENABLED
294        jtag_break <= `FALSE;
295        jtag_reset <= `FALSE;
296`endif
297`ifdef CFG_JTAG_UART_ENABLED
298        uart_tx_byte <= 8'h00;
299        uart_tx_valid <= `FALSE;
300        uart_rx_byte <= 8'h00;
301        uart_rx_valid <= `FALSE;
302`endif
303    end
304    else
305    begin
306`ifdef CFG_JTAG_UART_ENABLED
307        if ((csr_write_enable == `TRUE) && (stall_x == `FALSE))
308        begin
309            case (csr)
310            `LM32_CSR_JTX:
311            begin
312                // Set flag indicating data is available
313                uart_tx_byte <= csr_write_data[`LM32_BYTE_0_RNG];
314                uart_tx_valid <= `TRUE;
315            end
316            `LM32_CSR_JRX:
317            begin
318                // Clear flag indidicating data has been received
319                uart_rx_valid <= `FALSE;
320            end
321            endcase
322        end
323`endif
324`ifdef CFG_DEBUG_ENABLED
325        // When an exception has occured, clear the requests
326        if (exception_q_w == `TRUE)
327        begin
328            jtag_break <= `FALSE;
329            jtag_reset <= `FALSE;
330        end
331`endif
332        case (state)
333        `LM32_JTAG_STATE_READ_COMMAND:
334        begin
335            // Wait for rx register to toggle which indicates new data is available
336            if (rx_toggle_r_r != rx_toggle_r_r_r)
337            begin
338                command <= rx_byte[7:4];
339                case (rx_addr)
340`ifdef CFG_DEBUG_ENABLED
341                `LM32_DP:
342                begin
343                    case (rx_byte[7:4])
344`ifdef CFG_HW_DEBUG_ENABLED
345                    `LM32_DP_READ_MEMORY:
346                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
347                    `LM32_DP_READ_SEQUENTIAL:
348                    begin
349                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
350                        state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
351                    end
352                    `LM32_DP_WRITE_MEMORY:
353                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
354                    `LM32_DP_WRITE_SEQUENTIAL:
355                    begin
356                        {jtag_byte_2, jtag_byte_3} <= {jtag_byte_2, jtag_byte_3} + 1'b1;
357                        state <= 5;
358                    end
359                    `LM32_DP_WRITE_CSR:
360                        state <= `LM32_JTAG_STATE_READ_BYTE_0;
361`endif
362                    `LM32_DP_BREAK:
363                    begin
364`ifdef CFG_JTAG_UART_ENABLED
365                        uart_rx_valid <= `FALSE;
366                        uart_tx_valid <= `FALSE;
367`endif
368                        jtag_break <= `TRUE;
369                    end
370                    `LM32_DP_RESET:
371                    begin
372`ifdef CFG_JTAG_UART_ENABLED
373                        uart_rx_valid <= `FALSE;
374                        uart_tx_valid <= `FALSE;
375`endif
376                        jtag_reset <= `TRUE;
377                    end
378                    endcase
379                end
380`endif
381`ifdef CFG_JTAG_UART_ENABLED
382                `LM32_TX:
383                begin
384                    uart_rx_byte <= rx_byte;
385                    uart_rx_valid <= `TRUE;
386                end
387                `LM32_RX:
388                begin
389                    jtag_reg_d <= uart_tx_byte;
390                    uart_tx_valid <= `FALSE;
391                end
392`endif
393                default:
394                    ;
395                endcase
396            end
397        end
398`ifdef CFG_HW_DEBUG_ENABLED
399        `LM32_JTAG_STATE_READ_BYTE_0:
400        begin
401            if (rx_toggle_r_r != rx_toggle_r_r_r)
402            begin
403                jtag_byte_0 <= rx_byte;
404                state <= `LM32_JTAG_STATE_READ_BYTE_1;
405            end
406        end
407        `LM32_JTAG_STATE_READ_BYTE_1:
408        begin
409            if (rx_toggle_r_r != rx_toggle_r_r_r)
410            begin
411                jtag_byte_1 <= rx_byte;
412                state <= `LM32_JTAG_STATE_READ_BYTE_2;
413            end
414        end
415        `LM32_JTAG_STATE_READ_BYTE_2:
416        begin
417            if (rx_toggle_r_r != rx_toggle_r_r_r)
418            begin
419                jtag_byte_2 <= rx_byte;
420                state <= `LM32_JTAG_STATE_READ_BYTE_3;
421            end
422        end
423        `LM32_JTAG_STATE_READ_BYTE_3:
424        begin
425            if (rx_toggle_r_r != rx_toggle_r_r_r)
426            begin
427                jtag_byte_3 <= rx_byte;
428                if (command == `LM32_DP_READ_MEMORY)
429                    state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
430                else
431                    state <= `LM32_JTAG_STATE_READ_BYTE_4;
432            end
433        end
434        `LM32_JTAG_STATE_READ_BYTE_4:
435        begin
436            if (rx_toggle_r_r != rx_toggle_r_r_r)
437            begin
438                jtag_byte_4 <= rx_byte;
439                state <= `LM32_JTAG_STATE_PROCESS_COMMAND;
440            end
441        end
442        `LM32_JTAG_STATE_PROCESS_COMMAND:
443        begin
444            case (command)
445            `LM32_DP_READ_MEMORY,
446            `LM32_DP_READ_SEQUENTIAL:
447            begin
448                jtag_read_enable <= `TRUE;
449                processing <= `TRUE;
450                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
451            end
452            `LM32_DP_WRITE_MEMORY,
453            `LM32_DP_WRITE_SEQUENTIAL:
454            begin
455                jtag_write_enable <= `TRUE;
456                processing <= `TRUE;
457                state <= `LM32_JTAG_STATE_WAIT_FOR_MEMORY;
458            end
459            `LM32_DP_WRITE_CSR:
460            begin
461                jtag_csr_write_enable <= `TRUE;
462                processing <= `TRUE;
463                state <= `LM32_JTAG_STATE_WAIT_FOR_CSR;
464            end
465            endcase
466        end
467        `LM32_JTAG_STATE_WAIT_FOR_MEMORY:
468        begin
469            if (jtag_access_complete == `TRUE)
470            begin
471                jtag_read_enable <= `FALSE;
472                jtag_reg_d <= jtag_read_data;
473                jtag_write_enable <= `FALSE;
474                processing <= `FALSE;
475                state <= `LM32_JTAG_STATE_READ_COMMAND;
476            end
477        end
478        `LM32_JTAG_STATE_WAIT_FOR_CSR:
479        begin
480            jtag_csr_write_enable <= `FALSE;
481            processing <= `FALSE;
482            state <= `LM32_JTAG_STATE_READ_COMMAND;
483        end
484`endif
485        endcase
486    end
487end
488  
489endmodule
490
491`endif
492

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