Root/lm32/logic/sakc/rtl/lm32/lm32_load_store_unit.v

1// =============================================================================
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9// Lattice Semiconductor Corporation.
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15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_load_store_unit.v
19// Title : Load and store unit
20// Dependencies : lm32_include.v
21// Version : 6.0.13
22// =============================================================================
23
24`include "lm32_include.v"
25
26/////////////////////////////////////////////////////
27// Module interface
28/////////////////////////////////////////////////////
29
30module lm32_load_store_unit (
31    // ----- Inputs -------
32    clk_i,
33    rst_i,
34    // From pipeline
35    stall_a,
36    stall_x,
37    stall_m,
38    kill_x,
39    kill_m,
40    exception_m,
41    store_operand_x,
42    load_store_address_x,
43    load_store_address_m,
44    load_store_address_w,
45    load_q_x,
46    load_q_m,
47    store_q_m,
48    sign_extend_x,
49    size_x,
50`ifdef CFG_DCACHE_ENABLED
51    dflush,
52`endif
53    // From Wishbone
54    d_dat_i,
55    d_ack_i,
56    d_err_i,
57    d_rty_i,
58    // ----- Outputs -------
59    // To pipeline
60`ifdef CFG_DCACHE_ENABLED
61    dcache_refill_request,
62    dcache_restart_request,
63    dcache_stall_request,
64    dcache_refilling,
65`endif
66    load_data_w,
67    stall_wb_load,
68    // To Wishbone
69    d_dat_o,
70    d_adr_o,
71    d_cyc_o,
72    d_sel_o,
73    d_stb_o,
74    d_we_o,
75    d_cti_o,
76    d_lock_o,
77    d_bte_o
78    );
79
80/////////////////////////////////////////////////////
81// Parameters
82/////////////////////////////////////////////////////
83
84parameter associativity = 1; // Associativity of the cache (Number of ways)
85parameter sets = 512; // Number of sets
86parameter bytes_per_line = 16; // Number of bytes per cache line
87parameter base_address = 0; // Base address of cachable memory
88parameter limit = 0; // Limit (highest address) of cachable memory
89
90// For bytes_per_line == 4, we set 1 so part-select range isn't reversed, even though not really used
91//localparam addr_offset_width = bytes_per_line == 4 ? 1 : clogb2(bytes_per_line)-1-2;
92localparam addr_offset_width = 2;
93localparam addr_offset_lsb = 2;
94localparam addr_offset_msb = (addr_offset_lsb+addr_offset_width-1);
95
96/////////////////////////////////////////////////////
97// Inputs
98/////////////////////////////////////////////////////
99
100input clk_i; // Clock
101input rst_i; // Reset
102
103input stall_a; // A stage stall
104input stall_x; // X stage stall
105input stall_m; // M stage stall
106input kill_x; // Kill instruction in X stage
107input kill_m; // Kill instruction in M stage
108input exception_m; // An exception occured in the M stage
109
110input [`LM32_WORD_RNG] store_operand_x; // Data read from register to store
111input [`LM32_WORD_RNG] load_store_address_x; // X stage load/store address
112input [`LM32_WORD_RNG] load_store_address_m; // M stage load/store address
113input [1:0] load_store_address_w; // W stage load/store address (only least two significant bits are needed)
114input load_q_x; // Load instruction in X stage
115input load_q_m; // Load instruction in M stage
116input store_q_m; // Store instruction in M stage
117input sign_extend_x; // Whether load instruction in X stage should sign extend or zero extend
118input [`LM32_SIZE_RNG] size_x; // Size of load or store (byte, hword, word)
119
120`ifdef CFG_DCACHE_ENABLED
121input dflush; // Flush the data cache
122`endif
123
124input [`LM32_WORD_RNG] d_dat_i; // Data Wishbone interface read data
125input d_ack_i; // Data Wishbone interface acknowledgement
126input d_err_i; // Data Wishbone interface error
127input d_rty_i; // Data Wishbone interface retry
128
129/////////////////////////////////////////////////////
130// Outputs
131/////////////////////////////////////////////////////
132
133`ifdef CFG_DCACHE_ENABLED
134output dcache_refill_request; // Request to refill data cache
135wire dcache_refill_request;
136output dcache_restart_request; // Request to restart the instruction that caused a data cache miss
137wire dcache_restart_request;
138output dcache_stall_request; // Data cache stall request
139wire dcache_stall_request;
140output dcache_refilling;
141wire dcache_refilling;
142`endif
143
144output [`LM32_WORD_RNG] load_data_w; // Result of a load instruction
145reg [`LM32_WORD_RNG] load_data_w;
146output stall_wb_load; // Request to stall pipeline due to a load from the Wishbone interface
147reg stall_wb_load;
148
149output [`LM32_WORD_RNG] d_dat_o; // Data Wishbone interface write data
150reg [`LM32_WORD_RNG] d_dat_o;
151output [`LM32_WORD_RNG] d_adr_o; // Data Wishbone interface address
152reg [`LM32_WORD_RNG] d_adr_o;
153output d_cyc_o; // Data Wishbone interface cycle
154reg d_cyc_o;
155output [`LM32_BYTE_SELECT_RNG] d_sel_o; // Data Wishbone interface byte select
156reg [`LM32_BYTE_SELECT_RNG] d_sel_o;
157output d_stb_o; // Data Wishbone interface strobe
158reg d_stb_o;
159output d_we_o; // Data Wishbone interface write enable
160reg d_we_o;
161output [`LM32_CTYPE_RNG] d_cti_o; // Data Wishbone interface cycle type
162wire [`LM32_CTYPE_RNG] d_cti_o;
163output d_lock_o; // Date Wishbone interface lock bus
164wire d_lock_o;
165output [`LM32_BTYPE_RNG] d_bte_o; // Data Wishbone interface burst type
166wire [`LM32_BTYPE_RNG] d_bte_o;
167
168/////////////////////////////////////////////////////
169// Internal nets and registers
170/////////////////////////////////////////////////////
171
172// Microcode pipeline registers - See inputs for description
173reg [`LM32_SIZE_RNG] size_m;
174reg [`LM32_SIZE_RNG] size_w;
175reg sign_extend_m;
176reg sign_extend_w;
177reg [`LM32_WORD_RNG] store_data_x;
178reg [`LM32_WORD_RNG] store_data_m;
179reg [`LM32_BYTE_SELECT_RNG] byte_enable_x;
180reg [`LM32_BYTE_SELECT_RNG] byte_enable_m;
181wire [`LM32_WORD_RNG] data_m;
182reg [`LM32_WORD_RNG] data_w;
183
184`ifdef CFG_DCACHE_ENABLED
185wire dcache_select_x; // Select data cache to load from / store to
186reg dcache_select_m;
187wire [`LM32_WORD_RNG] dcache_data_m; // Data read from cache
188wire [`LM32_WORD_RNG] dcache_refill_address; // Address to refill data cache from
189reg dcache_refill_ready; // Indicates the next word of refill data is ready
190wire last_word; // Indicates if this is the last word in the cache line
191wire [`LM32_WORD_RNG] first_address; // First cache refill address
192`endif
193`ifdef CFG_DRAM_ENABLED
194wire dram_select_x; // Select data RAM to load from / store to
195reg dram_select_m;
196wire [`LM32_WORD_RNG] dram_data_m; // Data read from data RAM
197wire [`LM32_WORD_RNG] dram_store_data_m; // Data to write to RAM
198`endif
199wire wb_select_x; // Select Wishbone to load from / store to
200reg wb_select_m;
201reg [`LM32_WORD_RNG] wb_data_m; // Data read from Wishbone
202reg wb_load_complete; // Indicates when a Wishbone load is complete
203
204/////////////////////////////////////////////////////
205// Functions
206/////////////////////////////////////////////////////
207
208`include "lm32_functions.v"
209
210/////////////////////////////////////////////////////
211// Instantiations
212/////////////////////////////////////////////////////
213
214`ifdef CFG_DRAM_ENABLED
215// Data RAM
216pmi_ram_dp_true #(
217    // ----- Parameters -------
218    .pmi_addr_depth_a (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
219    .pmi_addr_width_a ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
220    .pmi_data_width_a (`LM32_WORD_WIDTH),
221    .pmi_addr_depth_b (1 << (clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
222    .pmi_addr_width_b ((clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)),
223    .pmi_data_width_b (`LM32_WORD_WIDTH),
224    .pmi_regmode_a ("noreg"),
225    .pmi_regmode_b ("noreg"),
226    .pmi_gsr ("enable"),
227    .pmi_resetmode ("async"),
228    .pmi_init_file (`CFG_DRAM_INIT_FILE),
229    .pmi_init_file_format ("hex"),
230    .module_type ("pmi_ram_dp")
231  ) ram (
232    // ----- Inputs -------
233    .ClockA (clk_i),
234    .ClockB (clk_i),
235    .ResetA (rst_i),
236    .ResetB (rst_i),
237    .DataInA ({32{1'b0}}),
238    .DataInB (dram_store_data_m),
239    .AddressA (load_store_address_x[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
240    .AddressB (load_store_address_m[(clogb2(`CFG_DRAM_LIMIT/4-`CFG_DRAM_BASE_ADDRESS/4+1)-1)+2-1:2]),
241    .ClockEnA (!stall_x),
242    .ClockEnB (!stall_m),
243    .WrA (`FALSE),
244    .WrB (store_q_m),
245    // ----- Outputs -------
246    .QA (dram_data_m),
247    .QB ()
248    );
249`endif
250
251`ifdef CFG_DCACHE_ENABLED
252// Data cache
253lm32_dcache #(
254    .associativity (associativity),
255    .sets (sets),
256    .bytes_per_line (bytes_per_line),
257    .base_address (base_address),
258    .limit (limit)
259    ) dcache (
260    // ----- Inputs -----
261    .clk_i (clk_i),
262    .rst_i (rst_i),
263    .stall_a (stall_a),
264    .stall_x (stall_x),
265    .stall_m (stall_m),
266    .address_x (load_store_address_x),
267    .address_m (load_store_address_m),
268    .load_q_m (load_q_m & dcache_select_m),
269    .store_q_m (store_q_m),
270    .store_data (store_data_m),
271    .store_byte_select (byte_enable_m),
272    .refill_ready (dcache_refill_ready),
273    .refill_data (wb_data_m),
274    .dflush (dflush),
275    // ----- Outputs -----
276    .stall_request (dcache_stall_request),
277    .restart_request (dcache_restart_request),
278    .refill_request (dcache_refill_request),
279    .refill_address (dcache_refill_address),
280    .refilling (dcache_refilling),
281    .load_data (dcache_data_m)
282    );
283`endif
284
285/////////////////////////////////////////////////////
286// Combinational Logic
287/////////////////////////////////////////////////////
288
289// Select where data should be loaded from / stored to
290`ifdef CFG_DCACHE_ENABLED
291assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) && (load_store_address_x <= `CFG_DCACHE_LIMIT);
292//assign dcache_select_x = (load_store_address_x >= `CFG_DCACHE_BASE_ADDRESS) && ~|load_store_address_x[`LM32_WORD_WIDTH-1:clogb2(`CFG_DCACHE_LIMIT-`CFG_DCACHE_BASE_ADDRESS)-1];
293`endif
294`ifdef CFG_DRAM_ENABLED
295assign dram_select_x = (load_store_address_x >= `CFG_DRAM_BASE_ADDRESS) && (load_store_address_x <= `CFG_DRAM_LIMIT);
296`endif
297assign wb_select_x = `TRUE
298`ifdef CFG_DCACHE_ENABLED
299                     && !dcache_select_x
300`endif
301`ifdef CFG_DRAM_ENABLED
302                     && !dram_select_x
303`endif
304                     ;
305
306// Make sure data to store is in correct byte lane
307always @(*)
308begin
309    case (size_x)
310    `LM32_SIZE_BYTE: store_data_x = {4{store_operand_x[7:0]}};
311    `LM32_SIZE_HWORD: store_data_x = {2{store_operand_x[15:0]}};
312    `LM32_SIZE_WORD: store_data_x = store_operand_x;
313    default: store_data_x = {`LM32_WORD_WIDTH{1'bx}};
314    endcase
315end
316
317// Generate byte enable accoring to size of load or store and address being accessed
318always @(*)
319begin
320    casez ({size_x, load_store_address_x[1:0]})
321    {`LM32_SIZE_BYTE, 2'b11}: byte_enable_x = 4'b0001;
322    {`LM32_SIZE_BYTE, 2'b10}: byte_enable_x = 4'b0010;
323    {`LM32_SIZE_BYTE, 2'b01}: byte_enable_x = 4'b0100;
324    {`LM32_SIZE_BYTE, 2'b00}: byte_enable_x = 4'b1000;
325    {`LM32_SIZE_HWORD, 2'b1?}: byte_enable_x = 4'b0011;
326    {`LM32_SIZE_HWORD, 2'b0?}: byte_enable_x = 4'b1100;
327    {`LM32_SIZE_WORD, 2'b??}: byte_enable_x = 4'b1111;
328    default: byte_enable_x = 4'bxxxx;
329    endcase
330end
331
332`ifdef CFG_DRAM_ENABLED
333// Only replace selected bytes
334assign dram_store_data_m[`LM32_BYTE_0_RNG] = byte_enable_m[0] ? store_data_m[`LM32_BYTE_0_RNG] : dram_data_m[`LM32_BYTE_0_RNG];
335assign dram_store_data_m[`LM32_BYTE_1_RNG] = byte_enable_m[1] ? store_data_m[`LM32_BYTE_1_RNG] : dram_data_m[`LM32_BYTE_1_RNG];
336assign dram_store_data_m[`LM32_BYTE_2_RNG] = byte_enable_m[2] ? store_data_m[`LM32_BYTE_2_RNG] : dram_data_m[`LM32_BYTE_2_RNG];
337assign dram_store_data_m[`LM32_BYTE_3_RNG] = byte_enable_m[3] ? store_data_m[`LM32_BYTE_3_RNG] : dram_data_m[`LM32_BYTE_3_RNG];
338`endif
339
340// Select data from selected source
341`ifdef CFG_DCACHE_ENABLED
342`ifdef CFG_DRAM_ENABLED
343assign data_m = wb_select_m == `TRUE
344                ? wb_data_m
345                : dram_select_m == `TRUE
346                   ? dram_data_m
347                   : dcache_data_m;
348`else
349assign data_m = wb_select_m == `TRUE ? wb_data_m : dcache_data_m;
350`endif
351`else
352`ifdef CFG_DRAM_ENABLED
353assign data_m = wb_select_m == `TRUE ? wb_data_m : dram_data_m;
354`else
355assign data_m = wb_data_m;
356`endif
357`endif
358
359// Sub-word selection and sign/zero-extension for loads
360always @(*)
361begin
362    casez ({size_w, load_store_address_w[1:0]})
363    {`LM32_SIZE_BYTE, 2'b11}: load_data_w = {{24{sign_extend_w & data_w[7]}}, data_w[7:0]};
364    {`LM32_SIZE_BYTE, 2'b10}: load_data_w = {{24{sign_extend_w & data_w[15]}}, data_w[15:8]};
365    {`LM32_SIZE_BYTE, 2'b01}: load_data_w = {{24{sign_extend_w & data_w[23]}}, data_w[23:16]};
366    {`LM32_SIZE_BYTE, 2'b00}: load_data_w = {{24{sign_extend_w & data_w[31]}}, data_w[31:24]};
367    {`LM32_SIZE_HWORD, 2'b1?}: load_data_w = {{16{sign_extend_w & data_w[15]}}, data_w[15:0]};
368    {`LM32_SIZE_HWORD, 2'b0?}: load_data_w = {{16{sign_extend_w & data_w[31]}}, data_w[31:16]};
369    {`LM32_SIZE_WORD, 2'b??}: load_data_w = data_w;
370    default: load_data_w = {`LM32_WORD_WIDTH{1'bx}};
371    endcase
372end
373
374// Unused Wishbone signals
375assign d_cti_o = `LM32_CTYPE_WIDTH'd0;
376assign d_lock_o = `FALSE;
377assign d_bte_o = `LM32_BTYPE_WIDTH'd0;
378
379`ifdef CFG_DCACHE_ENABLED
380// Generate signal to indicate last word in cache line
381generate
382        if (bytes_per_line > 4)
383        begin
384assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:addr_offset_msb+1], {addr_offset_width{1'b0}}, 2'b00};
385assign last_word = (&d_adr_o[addr_offset_msb:addr_offset_lsb]) == 1'b1;
386        end
387        else
388        begin
389assign first_address = {dcache_refill_address[`LM32_WORD_WIDTH-1:2], 2'b00};
390assign last_word = `TRUE;
391        end
392endgenerate
393`endif
394
395/////////////////////////////////////////////////////
396// Sequential Logic
397/////////////////////////////////////////////////////
398
399// Data Wishbone interface
400always @(posedge clk_i `CFG_RESET_SENSITIVITY)
401begin
402    if (rst_i == `TRUE)
403    begin
404        d_cyc_o <= `FALSE;
405        d_stb_o <= `FALSE;
406        d_dat_o <= {`LM32_WORD_WIDTH{1'b0}};
407        d_adr_o <= {`LM32_WORD_WIDTH{1'b0}};
408        d_sel_o <= {`LM32_BYTE_SELECT_WIDTH{`FALSE}};
409        d_we_o <= `FALSE;
410        wb_data_m <= {`LM32_WORD_WIDTH{1'b0}};
411        wb_load_complete <= `FALSE;
412        stall_wb_load <= `FALSE;
413`ifdef CFG_DCACHE_ENABLED
414        dcache_refill_ready <= `FALSE;
415`endif
416    end
417    else
418    begin
419`ifdef CFG_DCACHE_ENABLED
420        // Refill ready should only be asserted for a single cycle
421        dcache_refill_ready <= `FALSE;
422`endif
423        // Is a Wishbone cycle already in progress?
424        if (d_cyc_o == `TRUE)
425        begin
426            // Is the cycle complete?
427            if ((d_ack_i == `TRUE) || (d_err_i == `TRUE))
428            begin
429`ifdef CFG_DCACHE_ENABLED
430                if ((dcache_refilling == `TRUE) && (!last_word))
431                begin
432                    // Fetch next word of cache line
433                    d_adr_o[addr_offset_msb:addr_offset_lsb] <= d_adr_o[addr_offset_msb:addr_offset_lsb] + 1'b1;
434                end
435                else
436`endif
437                begin
438                    // Refill/access complete
439                    d_cyc_o <= `FALSE;
440                    d_stb_o <= `FALSE;
441                end
442`ifdef CFG_DCACHE_ENABLED
443                // If we are performing a refill, indicate to cache next word of data is ready
444                dcache_refill_ready <= dcache_refilling;
445`endif
446                // Register data read from Wishbone interface
447                wb_data_m <= d_dat_i;
448                // Don't set when stores complete - otherwise we'll deadlock if load in m stage
449                wb_load_complete <= !d_we_o;
450            end
451            // synthesis translate_off
452            if (d_err_i == `TRUE)
453                $display ("Data bus error. Address: %x", d_adr_o);
454            // synthesis translate_on
455        end
456        else
457        begin
458`ifdef CFG_DCACHE_ENABLED
459            if (dcache_refill_request == `TRUE)
460            begin
461                // Start cache refill
462                d_adr_o <= first_address;
463                d_cyc_o <= `TRUE;
464                d_sel_o <= {`LM32_WORD_WIDTH/8{`TRUE}};
465                d_stb_o <= `TRUE;
466                d_we_o <= `FALSE;
467            end
468            else
469`endif
470                 if ( (store_q_m == `TRUE)
471                     && (stall_m == `FALSE)
472`ifdef CFG_DRAM_ENABLED
473                     && !dram_select_m
474`endif
475                    )
476            begin
477                // Data cache is write through, so all stores go to memory
478                d_dat_o <= store_data_m;
479                d_adr_o <= load_store_address_m;
480                d_cyc_o <= `TRUE;
481                d_sel_o <= byte_enable_m;
482                d_stb_o <= `TRUE;
483                d_we_o <= `TRUE;
484            end
485            else if ( (load_q_m == `TRUE)
486                     && (wb_select_m == `TRUE)
487                     && (wb_load_complete == `FALSE)
488                     /* stall_m will be TRUE, because stall_wb_load will be TRUE */
489                    )
490            begin
491                // Read requested address
492                stall_wb_load <= `FALSE;
493                d_adr_o <= load_store_address_m;
494                d_cyc_o <= `TRUE;
495                d_sel_o <= byte_enable_m;
496                d_stb_o <= `TRUE;
497                d_we_o <= `FALSE;
498            end
499        end
500        // Clear load/store complete flag when instruction leaves M stage
501        if (stall_m == `FALSE)
502            wb_load_complete <= `FALSE;
503        // When a Wishbone load first enters the M stage, we need to stall it
504        if ((load_q_x == `TRUE) && (wb_select_x == `TRUE) && (stall_x == `FALSE))
505            stall_wb_load <= `TRUE;
506        // Clear stall request if load instruction is killed
507        if ((kill_m == `TRUE) || (exception_m == `TRUE))
508            stall_wb_load <= `FALSE;
509    end
510end
511
512// Pipeline registers
513
514// X/M stage pipeline registers
515always @(posedge clk_i `CFG_RESET_SENSITIVITY)
516begin
517    if (rst_i == `TRUE)
518    begin
519        sign_extend_m <= `FALSE;
520        size_m <= 2'b00;
521        byte_enable_m <= `FALSE;
522        store_data_m <= {`LM32_WORD_WIDTH{1'b0}};
523`ifdef CFG_DCACHE_ENABLED
524        dcache_select_m <= `FALSE;
525`endif
526`ifdef CFG_DRAM_ENABLED
527        dram_select_m <= `FALSE;
528`endif
529        wb_select_m <= `FALSE;
530    end
531    else
532    begin
533        if (stall_m == `FALSE)
534        begin
535            sign_extend_m <= sign_extend_x;
536            size_m <= size_x;
537            byte_enable_m <= byte_enable_x;
538            store_data_m <= store_data_x;
539`ifdef CFG_DCACHE_ENABLED
540            dcache_select_m <= dcache_select_x;
541`endif
542`ifdef CFG_DRAM_ENABLED
543            dram_select_m <= dram_select_x;
544`endif
545            wb_select_m <= wb_select_x;
546        end
547    end
548end
549
550// M/W stage pipeline registers
551always @(posedge clk_i `CFG_RESET_SENSITIVITY)
552begin
553    if (rst_i == `TRUE)
554    begin
555        size_w <= 2'b00;
556        data_w <= {`LM32_WORD_WIDTH{1'b0}};
557        sign_extend_w <= `FALSE;
558    end
559    else
560    begin
561        size_w <= size_m;
562        data_w <= data_m;
563        sign_extend_w <= sign_extend_m;
564    end
565end
566
567/////////////////////////////////////////////////////
568// Behavioural Logic
569/////////////////////////////////////////////////////
570
571// synthesis translate_off
572
573// Check for non-aligned loads or stores
574always @(posedge clk_i)
575begin
576    if (((load_q_m == `TRUE) || (store_q_m == `TRUE)) && (stall_m == `FALSE))
577    begin
578        if ((size_m === `LM32_SIZE_HWORD) && (load_store_address_m[0] !== 1'b0))
579            $display ("Warning: Non-aligned halfword access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
580        if ((size_m === `LM32_SIZE_WORD) && (load_store_address_m[1:0] !== 2'b00))
581            $display ("Warning: Non-aligned word access. Address: 0x%0x Time: %0t.", load_store_address_m, $time);
582    end
583end
584
585// synthesis translate_on
586
587endmodule
588
589

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