Hardware Design: SIE
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| 1 | // ============================================================================= |
| 2 | // COPYRIGHT NOTICE |
| 3 | // Copyright 2006 (c) Lattice Semiconductor Corporation |
| 4 | // ALL RIGHTS RESERVED |
| 5 | // This confidential and proprietary software may be used only as authorised by |
| 6 | // a licensing agreement from Lattice Semiconductor Corporation. |
| 7 | // The entire notice above must be reproduced on all authorized copies and |
| 8 | // copies may only be made to the extent permitted by a licensing agreement from |
| 9 | // Lattice Semiconductor Corporation. |
| 10 | // |
| 11 | // Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada) |
| 12 | // 5555 NE Moore Court 408-826-6000 (other locations) |
| 13 | // Hillsboro, OR 97124 web : http://www.latticesemi.com/ |
| 14 | // U.S.A email: techsupport@latticesemi.com |
| 15 | // =============================================================================/ |
| 16 | // FILE DETAILS |
| 17 | // Project : LatticeMico32 |
| 18 | // File : lm32_logic_op.v |
| 19 | // Title : Logic operations (and / or / not etc) |
| 20 | // Dependencies : lm32_include.v |
| 21 | // Version : 6.1.17 |
| 22 | // ============================================================================= |
| 23 | |
| 24 | `include "lm32_include.v" |
| 25 | |
| 26 | ///////////////////////////////////////////////////// |
| 27 | // Module interface |
| 28 | ///////////////////////////////////////////////////// |
| 29 | |
| 30 | module lm32_logic_op ( |
| 31 | // ----- Inputs ------- |
| 32 | logic_op_x, |
| 33 | operand_0_x, |
| 34 | operand_1_x, |
| 35 | // ----- Outputs ------- |
| 36 | logic_result_x |
| 37 | ); |
| 38 | |
| 39 | ///////////////////////////////////////////////////// |
| 40 | // Inputs |
| 41 | ///////////////////////////////////////////////////// |
| 42 | |
| 43 | input [`LM32_LOGIC_OP_RNG] logic_op_x; |
| 44 | input [`LM32_WORD_RNG] operand_0_x; |
| 45 | input [`LM32_WORD_RNG] operand_1_x; |
| 46 | |
| 47 | ///////////////////////////////////////////////////// |
| 48 | // Outputs |
| 49 | ///////////////////////////////////////////////////// |
| 50 | |
| 51 | output [`LM32_WORD_RNG] logic_result_x; |
| 52 | reg [`LM32_WORD_RNG] logic_result_x; |
| 53 | |
| 54 | ///////////////////////////////////////////////////// |
| 55 | // Internal nets and registers |
| 56 | ///////////////////////////////////////////////////// |
| 57 | |
| 58 | integer logic_idx; |
| 59 | |
| 60 | ///////////////////////////////////////////////////// |
| 61 | // Combinational Logic |
| 62 | ///////////////////////////////////////////////////// |
| 63 | |
| 64 | always @* |
| 65 | begin |
| 66 | for(logic_idx = 0; logic_idx < `LM32_WORD_WIDTH; logic_idx = logic_idx + 1) |
| 67 | logic_result_x[logic_idx] = logic_op_x[{operand_1_x[logic_idx], operand_0_x[logic_idx]}]; |
| 68 | end |
| 69 | |
| 70 | endmodule |
| 71 | |
| 72 |
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