Root/lm32/logic/sakc/rtl/lm32/lm32_monitor.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_monitor.v
19// Title : Debug monitor memory Wishbone interface
20// Version : 6.1.17
21// =============================================================================
22
23`include "system_conf.v"
24`include "lm32_include.v"
25
26/////////////////////////////////////////////////////
27// Module interface
28/////////////////////////////////////////////////////
29
30module lm32_monitor (
31    // ----- Inputs -------
32    clk_i,
33    rst_i,
34    MON_ADR_I,
35    MON_CYC_I,
36    MON_DAT_I,
37    MON_SEL_I,
38    MON_STB_I,
39    MON_WE_I,
40    MON_LOCK_I,
41    MON_CTI_I,
42    MON_BTE_I,
43    // ----- Outputs -------
44    MON_ACK_O,
45    MON_RTY_O,
46    MON_DAT_O,
47    MON_ERR_O
48    );
49
50/////////////////////////////////////////////////////
51// Inputs
52/////////////////////////////////////////////////////
53
54input clk_i; // Wishbone clock
55input rst_i; // Wishbone reset
56input [`LM32_WORD_RNG] MON_ADR_I; // Wishbone address
57input MON_STB_I; // Wishbone strobe
58input MON_CYC_I; // Wishbone cycle
59input [`LM32_WORD_RNG] MON_DAT_I; // Wishbone write data
60input [`LM32_BYTE_SELECT_RNG] MON_SEL_I; // Wishbone byte select
61input MON_WE_I; // Wishbone write enable
62input MON_LOCK_I; // Wishbone locked transfer
63input [`LM32_CTYPE_RNG] MON_CTI_I; // Wishbone cycle type
64input [`LM32_BTYPE_RNG] MON_BTE_I; // Wishbone burst type
65   
66/////////////////////////////////////////////////////
67// Outputs
68/////////////////////////////////////////////////////
69
70output MON_ACK_O; // Wishbone acknowlege
71reg MON_ACK_O;
72output [`LM32_WORD_RNG] MON_DAT_O; // Wishbone data output
73reg [`LM32_WORD_RNG] MON_DAT_O;
74output MON_RTY_O; // Wishbone retry
75wire MON_RTY_O;
76output MON_ERR_O; // Wishbone error
77wire MON_ERR_O;
78   
79/////////////////////////////////////////////////////
80// Internal nets and registers
81/////////////////////////////////////////////////////
82
83reg [1:0] state; // Current state of FSM
84wire [`LM32_WORD_RNG] data; // Data read from RAM
85reg write_enable; // RAM write enable
86reg [`LM32_WORD_RNG] write_data; // RAM write data
87 
88/////////////////////////////////////////////////////
89// Instantiations
90/////////////////////////////////////////////////////
91
92lm32_monitor_ram ram (
93    // ----- Inputs -------
94    .ClockA (clk_i),
95    .ClockB (clk_i),
96    .ResetA (rst_i),
97    .ResetB (rst_i),
98    .ClockEnA (`TRUE),
99    .ClockEnB (`FALSE),
100    .AddressA (MON_ADR_I[10:2]),
101    .DataInA (write_data),
102    .WrA (write_enable),
103    .WrB (`FALSE),
104    // ----- Outputs -------
105    .QA (data)
106    );
107
108/////////////////////////////////////////////////////
109// Combinational Logic
110/////////////////////////////////////////////////////
111
112assign MON_RTY_O = `FALSE;
113assign MON_ERR_O = `FALSE;
114
115/////////////////////////////////////////////////////
116// Sequential Logic
117/////////////////////////////////////////////////////
118
119always @(posedge clk_i `CFG_RESET_SENSITIVITY)
120begin
121    if (rst_i == `TRUE)
122    begin
123        write_enable <= `FALSE;
124        MON_ACK_O <= `FALSE;
125        MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
126        state <= 2'b00;
127    end
128    else
129    begin
130        case (state)
131        2'b00:
132        begin
133            // Wait for a Wishbone access
134            if ((MON_STB_I == `TRUE) && (MON_CYC_I == `TRUE))
135                state <= 2'b01;
136        end
137        2'b01:
138        begin
139            // Output read data to Wishbone
140            MON_ACK_O <= `TRUE;
141            MON_DAT_O <= data;
142            // Sub-word writes are performed using read-modify-write
143            // as the Lattice EBRs don't support byte enables
144            if (MON_WE_I == `TRUE)
145                write_enable <= `TRUE;
146            write_data[7:0] <= MON_SEL_I[0] ? MON_DAT_I[7:0] : data[7:0];
147            write_data[15:8] <= MON_SEL_I[1] ? MON_DAT_I[15:8] : data[15:8];
148            write_data[23:16] <= MON_SEL_I[2] ? MON_DAT_I[23:16] : data[23:16];
149            write_data[31:24] <= MON_SEL_I[3] ? MON_DAT_I[31:24] : data[31:24];
150            state <= 2'b10;
151        end
152        2'b10:
153        begin
154            // Wishbone access occurs in this cycle
155            write_enable <= `FALSE;
156            MON_ACK_O <= `FALSE;
157            MON_DAT_O <= {`LM32_WORD_WIDTH{1'bx}};
158            state <= 2'b00;
159        end
160        endcase
161    end
162end
163
164endmodule
165

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