Root/lm32/logic/sakc/rtl/lm32/lm32_ram.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_ram.v
19// Title : Pseudo dual-port RAM.
20// Version : 6.1.17
21// =============================================================================
22
23`include "lm32_include.v"
24
25/////////////////////////////////////////////////////
26// Module interface
27/////////////////////////////////////////////////////
28
29module lm32_ram (
30    // ----- Inputs -------
31    read_clk,
32    write_clk,
33    reset,
34    enable_read,
35    read_address,
36    enable_write,
37    write_address,
38    write_data,
39    write_enable,
40    // ----- Outputs -------
41    read_data
42    );
43
44/////////////////////////////////////////////////////
45// Parameters
46/////////////////////////////////////////////////////
47
48parameter data_width = 1; // Width of the data ports
49parameter address_width = 1; // Width of the address ports
50
51/////////////////////////////////////////////////////
52// Inputs
53/////////////////////////////////////////////////////
54
55input read_clk; // Read clock
56input write_clk; // Write clock
57input reset; // Reset
58
59input enable_read; // Access enable
60input [address_width-1:0] read_address; // Read/write address
61input enable_write; // Access enable
62input [address_width-1:0] write_address;// Read/write address
63input [data_width-1:0] write_data; // Data to write to specified address
64input write_enable; // Write enable
65
66/////////////////////////////////////////////////////
67// Outputs
68/////////////////////////////////////////////////////
69
70output [data_width-1:0] read_data; // Data read from specified addess
71wire [data_width-1:0] read_data;
72    
73/////////////////////////////////////////////////////
74// Internal nets and registers
75/////////////////////////////////////////////////////
76
77reg [data_width-1:0] mem[0:(1<<address_width)-1]; // The RAM
78reg [address_width-1:0] ra; // Registered read address
79
80/////////////////////////////////////////////////////
81// Combinational Logic
82/////////////////////////////////////////////////////
83
84// Read port
85assign read_data = mem[ra];
86
87/////////////////////////////////////////////////////
88// Sequential Logic
89/////////////////////////////////////////////////////
90
91// Write port
92always @(posedge write_clk)
93begin
94    if ((write_enable == `TRUE) && (enable_write == `TRUE))
95        mem[write_address] <= write_data;
96end
97
98// Register read address for use on next cycle
99always @(posedge read_clk)
100begin
101    if (enable_read)
102        ra <= read_address;
103end
104
105endmodule
106

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