Root/lm32/logic/sakc/rtl/lm32/lm32_simtrace.v

1// =============================================================================/
2// FILE DETAILS
3// Project : LatticeMico32
4// File : lm32_simtrace.v
5// Title : Trace excecution in simulation
6// Dependencies : lm32_include.v
7// Version : soc-lm32 only
8// =============================================================================
9
10`include "lm32_include.v"
11
12// Index of opcode field in an instruction
13`define LM32_OPCODE_RNG 31:26
14`define LM32_OP_RNG 30:26
15
16/////////////////////////////////////////////////////
17// Module interface
18/////////////////////////////////////////////////////
19
20module lm32_simtrace (
21    // ----- Inputs -------
22    clk_i,
23    rst_i,
24    // From pipeline
25    stall_x,
26    stall_m,
27    valid_w,
28    kill_w,
29    instruction_d,
30    pc_w
31    );
32
33/////////////////////////////////////////////////////
34// Inputs
35/////////////////////////////////////////////////////
36
37input clk_i;
38input rst_i;
39input stall_x; //
40input stall_m; //
41input valid_w; //
42input kill_w; //
43input [`LM32_INSTRUCTION_RNG] instruction_d; // Instruction to decode
44input [`LM32_PC_RNG] pc_w; // PC of instruction in D stage
45
46/////////////////////////////////////////////////////
47// Internal nets and registers
48/////////////////////////////////////////////////////
49reg [`LM32_INSTRUCTION_RNG] instruction_x; // Instruction to decode
50reg [`LM32_INSTRUCTION_RNG] instruction_m; // Instruction to decode
51reg [`LM32_INSTRUCTION_RNG] instruction; // Instruction to decode
52
53wire [`LM32_WORD_RNG] extended_immediate; // Zero or sign extended immediate
54wire [`LM32_WORD_RNG] high_immediate; // Immedate as high 16 bits
55wire [`LM32_WORD_RNG] immediate; // Immedate as high 16 bits
56wire [`LM32_WORD_RNG] call_immediate; // Call immediate
57wire [`LM32_WORD_RNG] branch_immediate; // Conditional branch immediate
58
59/////////////////////////////////////////////////////
60// Functions
61/////////////////////////////////////////////////////
62
63`include "lm32_functions.v"
64
65
66wire [4:0] r3 = instruction[25:21];
67wire [4:0] r2 = instruction[20:16];
68wire [4:0] r1 = instruction[15:11];
69
70wire [ 4:0] imm5 = instruction[ 4:0];
71wire [15:0] imm16 = instruction[15:0];
72wire [26:0] imm27 = instruction[26:0];
73
74//assign high_imm = {instruction[15:0], 16'h0000};
75wire [`LM32_PC_RNG] call_imm = {{ 4{instruction[25]}}, instruction[25:0]};
76wire [`LM32_PC_RNG] branch_imm = {{14{instruction[15]}}, instruction[15:0] };
77
78// synopsys translate_off
79
80always @(posedge clk_i)
81begin
82    if (stall_x == `FALSE)
83        instruction_x <= instruction_d;
84    if (stall_m == `FALSE)
85        instruction_m <= instruction_x;
86    instruction <= instruction_m;
87
88    if ((valid_w == `TRUE) && (!kill_w)) begin
89        // $write ( $stime/10 );
90        $writeh( " [", pc_w << 2);
91        $writeh( "]\t" );
92
93        case ( instruction[`LM32_OPCODE_RNG] )
94            6'h00: $display( "srui r%0d, r%0d, 0x%0x", r2, r3, imm5 );
95            6'h01: $display( "nori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
96            6'h02: $display( "muli r%0d, r%0d, 0x%0x", r2, r3, imm16 );
97            6'h03: $display( "sh (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
98            6'h04: $display( "lb r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
99            6'h05: $display( "sri r%0d, r%0d, 0x%0x", r2, r3, imm16 );
100            6'h06: $display( "xori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
101            6'h07: $display( "lh r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
102            6'h08: $display( "andi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
103            6'h09: $display( "xnori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
104            6'h0a: $display( "lw r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
105            6'h0b: $display( "lhu r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
106            6'h0c: $display( "sb (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
107            6'h0d: $display( "addi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
108            6'h0e: $display( "ori r%0d, r%0d, 0x%0x", r2, r3, imm16 );
109            6'h0f: $display( "sli r%0d, r%0d, 0x%0x", r2, r3, imm5 );
110            6'h10: $display( "lbu r%0d, (r%0d + 0x%0x)", r2, r3, imm16 );
111            6'h11: $display( "be r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
112            6'h12: $display( "bg r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
113            6'h13: $display( "bge r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
114            6'h14: $display( "bgeu r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
115            6'h15: $display( "bgu r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
116            6'h16: $display( "sw (r%0d + 0x%0x), r%0d", r3, r2, imm16 );
117            6'h17: $display( "bne r%0d, r%0d, 0x%x", r2, r3, (pc_w + branch_imm ) << 2 );
118            6'h18: $display( "andhi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
119            6'h19: $display( "cmpei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
120            6'h1a: $display( "cmpgi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
121            6'h1b: $display( "cmpgei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
122            6'h1c: $display( "cmpgeui r%0d, r%0d, 0x%0x", r2, r3, imm16 );
123            6'h1d: $display( "cmpgui r%0d, r%0d, 0x%0x", r2, r3, imm16 );
124            6'h1e: $display( "orhi r%0d, r%0d, 0x%0x", r2, r3, imm16 );
125            6'h1f: $display( "cmpnei r%0d, r%0d, 0x%0x", r2, r3, imm16 );
126            6'h20: $display( "sru r%0d, r%0d, r%0d", r1, r3, r2 );
127            6'h21: $display( "nor r%0d, r%0d, r%0d", r1, r3, r2 );
128            6'h22: $display( "mul r%0d, r%0d, r%0d", r1, r3, r2 );
129            6'h23: $display( "divu r%0d, r%0d, r%0d", r1, r3, r2 );
130            6'h24: $display( "rcsr r%0d, csr%0d", r1, r3 );
131            6'h25: $display( "sr r%0d, r%0d, r%0d", r1, r3, r2 );
132            6'h26: $display( "xor r%0d, r%0d, r%0d", r1, r3, r2 );
133            6'h27: $display( "div (XXX not documented XXX)" );
134            6'h28: $display( "and r%0d, r%0d, r%0d", r1, r3, r2 );
135            6'h29: $display( "xnor r%0d, r%0d, r%0d", r1, r3, r2 );
136            6'h2a: $display( "XXX" );
137            6'h2b: $display( "raise (XXX: scall or break)" );
138            6'h2c: $display( "sextb r%0d, r%0d", r1, r3 );
139            6'h2d: $display( "add r%0d, r%0d, r%0d", r1, r3, r2 );
140            6'h2e: $display( "or r%0d, r%0d, r%0d", r1, r3, r2 );
141            6'h2f: $display( "sl r%0d, r%0d, r%0d", r1, r3, r2 );
142            6'h30: $display( "b r%0d", r3 );
143            6'h31: $display( "modu r%0d, r%0d, r%0d", r1, r3, r2 );
144            6'h32: $display( "sub r%0d, r%0d, r%0d", r1, r3, r2 );
145            6'h33: $display( "XXX" );
146            6'h34: $display( "wcsr csr%0d, r%0d", r3, r2 );
147            6'h35: $display( "modu r%0d, r%0d, r%0d", r1, r3, r2 );
148            6'h36: $display( "call r%0d", r3 );
149            6'h37: $display( "sexth r%0d, r%0d", r1, r3 );
150            6'h38: $display( "bi 0x%x", (pc_w + call_imm) << 2 );
151            6'h39: $display( "cmpe r%0d, r%0d, r%0d", r1, r3, r2 );
152            6'h3a: $display( "cmpg r%0d, r%0d, r%0d", r1, r3, r2 );
153            6'h3b: $display( "cmpge r%0d, r%0d, r%0d", r1, r3, r2 );
154            6'h3c: $display( "cmpgeu r%0d, r%0d, r%0d", r1, r3, r2 );
155            6'h3d: $display( "cmpgu r%0d, r%0d, r%0d", r1, r3, r2 );
156            6'h3e: $display( "calli 0x%x", (pc_w + call_imm) << 2 );
157            6'h3f: $display( "cmpne r%0d, r%0d, r%0d", r1, r3, r2 );
158        endcase
159    end
160end
161
162// synopsys translate_on
163
164endmodule
165
166

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