Root/lm32/logic/sakc/rtl/lm32/lm32_top.v

1// =============================================================================
2// COPYRIGHT NOTICE
3// Copyright 2006 (c) Lattice Semiconductor Corporation
4// ALL RIGHTS RESERVED
5// This confidential and proprietary software may be used only as authorised by
6// a licensing agreement from Lattice Semiconductor Corporation.
7// The entire notice above must be reproduced on all authorized copies and
8// copies may only be made to the extent permitted by a licensing agreement from
9// Lattice Semiconductor Corporation.
10//
11// Lattice Semiconductor Corporation TEL : 1-800-Lattice (USA and Canada)
12// 5555 NE Moore Court 408-826-6000 (other locations)
13// Hillsboro, OR 97124 web : http://www.latticesemi.com/
14// U.S.A email: techsupport@latticesemi.com
15// =============================================================================/
16// FILE DETAILS
17// Project : LatticeMico32
18// File : lm32_top.v
19// Title : Top-level of CPU.
20// Dependencies : lm32_include.v
21// Version : 6.1.17
22// =============================================================================
23
24`include "lm32_include.v"
25
26/////////////////////////////////////////////////////
27// Module interface
28/////////////////////////////////////////////////////
29
30module lm32_top (
31    // ----- Inputs -------
32    clk_i,
33    rst_i,
34    // From external devices
35`ifdef CFG_INTERRUPTS_ENABLED
36    interrupt_n,
37`endif
38    // From user logic
39`ifdef CFG_USER_ENABLED
40    user_result,
41    user_complete,
42`endif
43`ifdef CFG_IWB_ENABLED
44    // Instruction Wishbone master
45    I_DAT_I,
46    I_ACK_I,
47    I_ERR_I,
48    I_RTY_I,
49`endif
50    // Data Wishbone master
51    D_DAT_I,
52    D_ACK_I,
53    D_ERR_I,
54    D_RTY_I,
55    // Debug Slave port WishboneInterface
56    DEBUG_ADR_I,
57    DEBUG_DAT_I,
58    DEBUG_SEL_I,
59    DEBUG_WE_I,
60    DEBUG_CTI_I,
61    DEBUG_BTE_I,
62    DEBUG_LOCK_I,
63    DEBUG_CYC_I,
64    DEBUG_STB_I,
65    // ----- Outputs -------
66`ifdef CFG_USER_ENABLED
67    user_valid,
68    user_opcode,
69    user_operand_0,
70    user_operand_1,
71`endif
72`ifdef CFG_IWB_ENABLED
73    // Instruction Wishbone master
74    I_DAT_O,
75    I_ADR_O,
76    I_CYC_O,
77    I_SEL_O,
78    I_STB_O,
79    I_WE_O,
80    I_CTI_O,
81    I_LOCK_O,
82    I_BTE_O,
83`endif
84    // Data Wishbone master
85    D_DAT_O,
86    D_ADR_O,
87    D_CYC_O,
88    D_SEL_O,
89    D_STB_O,
90    D_WE_O,
91    D_CTI_O,
92    D_LOCK_O,
93    D_BTE_O,
94    // Debug Slave port WishboneInterface
95    DEBUG_ACK_O,
96    DEBUG_ERR_O,
97    DEBUG_RTY_O,
98    DEBUG_DAT_O
99    );
100
101/////////////////////////////////////////////////////
102// Inputs
103/////////////////////////////////////////////////////
104
105input clk_i; // Clock
106input rst_i; // Reset
107
108`ifdef CFG_INTERRUPTS_ENABLED
109input [`LM32_INTERRUPT_RNG] interrupt_n; // Interrupt pins, active-low
110`endif
111
112`ifdef CFG_USER_ENABLED
113input [`LM32_WORD_RNG] user_result; // User-defined instruction result
114input user_complete; // Indicates the user-defined instruction result is valid
115`endif
116
117`ifdef CFG_IWB_ENABLED
118input [`LM32_WORD_RNG] I_DAT_I; // Instruction Wishbone interface read data
119input I_ACK_I; // Instruction Wishbone interface acknowledgement
120input I_ERR_I; // Instruction Wishbone interface error
121input I_RTY_I; // Instruction Wishbone interface retry
122`endif
123
124input [`LM32_WORD_RNG] D_DAT_I; // Data Wishbone interface read data
125input D_ACK_I; // Data Wishbone interface acknowledgement
126input D_ERR_I; // Data Wishbone interface error
127input D_RTY_I; // Data Wishbone interface retry
128
129input [`LM32_WORD_RNG] DEBUG_ADR_I; // Debug monitor Wishbone interface address
130input [`LM32_WORD_RNG] DEBUG_DAT_I; // Debug monitor Wishbone interface write data
131input [`LM32_BYTE_SELECT_RNG] DEBUG_SEL_I; // Debug monitor Wishbone interface byte select
132input DEBUG_WE_I; // Debug monitor Wishbone interface write enable
133input [`LM32_CTYPE_RNG] DEBUG_CTI_I; // Debug monitor Wishbone interface cycle type
134input [`LM32_BTYPE_RNG] DEBUG_BTE_I; // Debug monitor Wishbone interface burst type
135input DEBUG_LOCK_I; // Debug monitor Wishbone interface locked transfer
136input DEBUG_CYC_I; // Debug monitor Wishbone interface cycle
137input DEBUG_STB_I; // Debug monitor Wishbone interface strobe
138
139/////////////////////////////////////////////////////
140// Outputs
141/////////////////////////////////////////////////////
142
143`ifdef CFG_USER_ENABLED
144output user_valid; // Indicates that user_opcode and user_operand_* are valid
145wire user_valid;
146output [`LM32_USER_OPCODE_RNG] user_opcode; // User-defined instruction opcode
147reg [`LM32_USER_OPCODE_RNG] user_opcode;
148output [`LM32_WORD_RNG] user_operand_0; // First operand for user-defined instruction
149wire [`LM32_WORD_RNG] user_operand_0;
150output [`LM32_WORD_RNG] user_operand_1; // Second operand for user-defined instruction
151wire [`LM32_WORD_RNG] user_operand_1;
152`endif
153
154`ifdef CFG_IWB_ENABLED
155output [`LM32_WORD_RNG] I_DAT_O; // Instruction Wishbone interface write data
156wire [`LM32_WORD_RNG] I_DAT_O;
157output [`LM32_WORD_RNG] I_ADR_O; // Instruction Wishbone interface address
158wire [`LM32_WORD_RNG] I_ADR_O;
159output I_CYC_O; // Instruction Wishbone interface cycle
160wire I_CYC_O;
161output [`LM32_BYTE_SELECT_RNG] I_SEL_O; // Instruction Wishbone interface byte select
162wire [`LM32_BYTE_SELECT_RNG] I_SEL_O;
163output I_STB_O; // Instruction Wishbone interface strobe
164wire I_STB_O;
165output I_WE_O; // Instruction Wishbone interface write enable
166wire I_WE_O;
167output [`LM32_CTYPE_RNG] I_CTI_O; // Instruction Wishbone interface cycle type
168wire [`LM32_CTYPE_RNG] I_CTI_O;
169output I_LOCK_O; // Instruction Wishbone interface lock bus
170wire I_LOCK_O;
171output [`LM32_BTYPE_RNG] I_BTE_O; // Instruction Wishbone interface burst type
172wire [`LM32_BTYPE_RNG] I_BTE_O;
173`endif
174
175output [`LM32_WORD_RNG] D_DAT_O; // Data Wishbone interface write data
176wire [`LM32_WORD_RNG] D_DAT_O;
177output [`LM32_WORD_RNG] D_ADR_O; // Data Wishbone interface address
178wire [`LM32_WORD_RNG] D_ADR_O;
179output D_CYC_O; // Data Wishbone interface cycle
180wire D_CYC_O;
181output [`LM32_BYTE_SELECT_RNG] D_SEL_O; // Data Wishbone interface byte select
182wire [`LM32_BYTE_SELECT_RNG] D_SEL_O;
183output D_STB_O; // Data Wishbone interface strobe
184wire D_STB_O;
185output D_WE_O; // Data Wishbone interface write enable
186wire D_WE_O;
187output [`LM32_CTYPE_RNG] D_CTI_O; // Data Wishbone interface cycle type
188wire [`LM32_CTYPE_RNG] D_CTI_O;
189output D_LOCK_O; // Date Wishbone interface lock bus
190wire D_LOCK_O;
191output [`LM32_BTYPE_RNG] D_BTE_O; // Data Wishbone interface burst type
192wire [`LM32_BTYPE_RNG] D_BTE_O;
193
194output DEBUG_ACK_O; // Debug monitor Wishbone ack
195wire DEBUG_ACK_O;
196output DEBUG_ERR_O; // Debug monitor Wishbone error
197wire DEBUG_ERR_O;
198output DEBUG_RTY_O; // Debug monitor Wishbone retry
199wire DEBUG_RTY_O;
200output [`LM32_WORD_RNG] DEBUG_DAT_O; // Debug monitor Wishbone read data
201wire [`LM32_WORD_RNG] DEBUG_DAT_O;
202  
203/////////////////////////////////////////////////////
204// Internal nets and registers
205/////////////////////////////////////////////////////
206 
207`ifdef CFG_JTAG_ENABLED
208// Signals between JTAG interface and CPU
209wire [`LM32_BYTE_RNG] jtag_reg_d;
210wire [`LM32_BYTE_RNG] jtag_reg_q;
211wire jtag_update;
212wire [2:0] jtag_reg_addr_d;
213wire [2:0] jtag_reg_addr_q;
214wire jtck;
215wire jrstn;
216`endif
217
218`ifdef CFG_TRACE_ENABLED
219// PC trace signals
220wire [`LM32_PC_RNG] trace_pc; // PC to trace (address of next non-sequential instruction)
221wire trace_pc_valid; // Indicates that a new trace PC is valid
222wire trace_exception; // Indicates an exception has occured
223wire [`LM32_EID_RNG] trace_eid; // Indicates what type of exception has occured
224wire trace_eret; // Indicates an eret instruction has been executed
225`ifdef CFG_DEBUG_ENABLED
226wire trace_bret; // Indicates a bret instruction has been executed
227`endif
228`endif
229
230/////////////////////////////////////////////////////
231// Functions
232/////////////////////////////////////////////////////
233
234`include "lm32_functions.v"
235/////////////////////////////////////////////////////
236// Instantiations
237/////////////////////////////////////////////////////
238   
239// LM32 CPU
240lm32_cpu cpu (
241    // ----- Inputs -------
242    .clk_i (clk_i),
243`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
244    .clk_n_i (clk_n),
245`endif
246    .rst_i (rst_i),
247    // From external devices
248`ifdef CFG_INTERRUPTS_ENABLED
249    .interrupt_n (interrupt_n),
250`endif
251    // From user logic
252`ifdef CFG_USER_ENABLED
253    .user_result (user_result),
254    .user_complete (user_complete),
255`endif
256`ifdef CFG_JTAG_ENABLED
257    // From JTAG
258    .jtag_clk (jtck),
259    .jtag_update (jtag_update),
260    .jtag_reg_q (jtag_reg_q),
261    .jtag_reg_addr_q (jtag_reg_addr_q),
262`endif
263`ifdef CFG_IWB_ENABLED
264     // Instruction Wishbone master
265    .I_DAT_I (I_DAT_I),
266    .I_ACK_I (I_ACK_I),
267    .I_ERR_I (I_ERR_I),
268    .I_RTY_I (I_RTY_I),
269`endif
270    // Data Wishbone master
271    .D_DAT_I (D_DAT_I),
272    .D_ACK_I (D_ACK_I),
273    .D_ERR_I (D_ERR_I),
274    .D_RTY_I (D_RTY_I),
275    // ----- Outputs -------
276`ifdef CFG_TRACE_ENABLED
277    .trace_pc (trace_pc),
278    .trace_pc_valid (trace_pc_valid),
279    .trace_exception (trace_exception),
280    .trace_eid (trace_eid),
281    .trace_eret (trace_eret),
282`ifdef CFG_DEBUG_ENABLED
283    .trace_bret (trace_bret),
284`endif
285`endif
286`ifdef CFG_JTAG_ENABLED
287    .jtag_reg_d (jtag_reg_d),
288    .jtag_reg_addr_d (jtag_reg_addr_d),
289`endif
290`ifdef CFG_USER_ENABLED
291    .user_valid (user_valid),
292    .user_opcode (user_opcode),
293    .user_operand_0 (user_operand_0),
294    .user_operand_1 (user_operand_1),
295`endif
296`ifdef CFG_IWB_ENABLED
297    // Instruction Wishbone master
298    .I_DAT_O (I_DAT_O),
299    .I_ADR_O (I_ADR_O),
300    .I_CYC_O (I_CYC_O),
301    .I_SEL_O (I_SEL_O),
302    .I_STB_O (I_STB_O),
303    .I_WE_O (I_WE_O),
304    .I_CTI_O (I_CTI_O),
305    .I_LOCK_O (I_LOCK_O),
306    .I_BTE_O (I_BTE_O),
307    `endif
308    // Data Wishbone master
309    .D_DAT_O (D_DAT_O),
310    .D_ADR_O (D_ADR_O),
311    .D_CYC_O (D_CYC_O),
312    .D_SEL_O (D_SEL_O),
313    .D_STB_O (D_STB_O),
314    .D_WE_O (D_WE_O),
315    .D_CTI_O (D_CTI_O),
316    .D_LOCK_O (D_LOCK_O),
317    .D_BTE_O (D_BTE_O)
318    );
319
320`ifdef DEBUG_ROM
321// ROM monitor
322lm32_monitor debug_rom (
323    // ----- Inputs -------
324    .clk_i (clk_i),
325    .rst_i (rst_i),
326    .MON_ADR_I (DEBUG_ADR_I),
327    .MON_STB_I (DEBUG_STB_I),
328    .MON_CYC_I (DEBUG_CYC_I),
329    .MON_WE_I (DEBUG_WE_I),
330    .MON_SEL_I (DEBUG_SEL_I),
331    .MON_DAT_I (DEBUG_DAT_I),
332    .MON_CTI_I (DEBUG_CTI_I),
333    .MON_BTE_I (DEBUG_BTE_I),
334    .MON_LOCK_I (DEBUG_LOCK_I),
335    // ----- Outputs ------
336    .MON_RTY_O (DEBUG_RTY_O),
337    .MON_ERR_O (DEBUG_ERR_O),
338    .MON_ACK_O (DEBUG_ACK_O),
339    .MON_DAT_O (DEBUG_DAT_O)
340    );
341`endif
342   
343`ifdef CFG_JTAG_ENABLED
344// JTAG cores
345jtag_cores jtag_cores (
346    // ----- Inputs -----
347`ifdef INCLUDE_LM32
348    .reg_d (jtag_reg_d),
349    .reg_addr_d (jtag_reg_addr_d),
350`endif
351`ifdef INCLUDE_SPI
352    .spi_q (spi_q),
353`endif
354    // ----- Outputs -----
355`ifdef INCLUDE_LM32
356    .reg_update (jtag_update),
357    .reg_q (jtag_reg_q),
358    .reg_addr_q (jtag_reg_addr_q),
359`endif
360`ifdef INCLUDE_SPI
361    .spi_c (spi_c),
362    .spi_d (spi_d),
363    .spi_sn (spi_sn),
364`endif
365    .jtck (jtck),
366    .jrstn (jrstn)
367    );
368`endif
369   
370endmodule
371

Archive Download this file

Branches:
master



interactive