Root/lm32/logic/sakc/rtl/lm32/spiprog.v

1//---------------------------------------------------------------------------
2//
3//Name : SPIPROG.v
4//
5//Description:
6//
7// This module contains the ER2 regsiters of SPI Serial FLASH programmer IP
8// core. There are only three ER2 registers, one control register and two
9// data registers, in this IP core. The control register is a 8-bit wide
10// register for selecting which data register will be accessed when the
11// Control/Data# bit in ER1 register is low. Data register 0 is a readonly
12// ID register. It is composed of three register fields -- an 8-bit
13// "implementer", a 16-bit "IP_functionality", and a 12-bit "revision".
14// Data register 1 is a variable length register for sending commands to or
15// receiving readback data from the SPI Serial FLASH device.
16//
17//$Log: spiprog.vhd,v $
18//Revision 1.2 2004-09-09 11:43:26-07 jhsin
19//1. Reduced the the ID register (DR0) length from 36 bits to 8 bits.
20//2. Same as TYPEA and TYPEB modules, use falling edge clock
21// for all TCK Flip-Flops.
22//
23//Revision 1.1 2004-08-12 13:22:05-07 jhsin
24//Added 7 delay Flip-Flops so that the DR1 readback data from SPI Serial FLASH is in the byte boundary.
25//
26//Revision 1.0 2004-08-03 18:35:56-07 jhsin
27//Initial revision
28//
29//
30//$Header: \\\\hqfs2\\ip\040cores\\rcs\\hqfs2\\ip\040cores\\rcswork\\isptracy\\VHDL\\Implementation\\spiprog.vhd,v 1.2 2004-09-09 11:43:26-07 jhsin Exp $
31//
32//Copyright (C) 2004 Lattice Semiconductor Corp. All rights reserved.
33//
34//---------------------------------------------------------------------------
35
36module SPIPROG (input JTCK ,
37        input JTDI ,
38        output JTDO2 ,
39        input JSHIFT ,
40        input JUPDATE ,
41        input JRSTN ,
42        input JCE2 ,
43        input SPIPROG_ENABLE ,
44        input CONTROL_DATAN ,
45        output SPI_C ,
46        output SPI_D ,
47        output SPI_SN ,
48        input SPI_Q);
49
50   wire er2Cr_enable ;
51   wire er2Dr0_enable;
52   wire er2Dr1_enable;
53   
54   wire tdo_er2Cr ;
55   wire tdo_er2Dr0;
56   wire tdo_er2Dr1;
57   
58   wire [7:0] encodedDrSelBits ;
59   wire [8:0] er2CrTdiBit ;
60   wire [8:0] er2Dr0TdiBit ;
61   
62   wire captureDrER2;
63   reg spi_s ;
64   reg [6:0] spi_q_dly;
65   
66   wire [7:0] ip_functionality_id;
67   
68   genvar i;
69   
70   // ------ Control Register 0 ------
71   
72   assign er2Cr_enable = JCE2 & SPIPROG_ENABLE & CONTROL_DATAN;
73   
74   assign tdo_er2Cr = er2CrTdiBit[0];
75   
76   // CR_BIT0_BIT7
77   generate
78      for(i=0; i<=7; i=i+1)
79    begin:CR_BIT0_BIT7
80       TYPEA BIT_N (.CLK (JTCK),
81            .RESET_N (JRSTN),
82            .CLKEN (er2Cr_enable),
83            .TDI (er2CrTdiBit[i + 1]),
84            .TDO (er2CrTdiBit[i]),
85            .DATA_OUT (encodedDrSelBits[i]),
86            .DATA_IN (encodedDrSelBits[i]),
87            .CAPTURE_DR (captureDrER2),
88            .UPDATE_DR (JUPDATE));
89    end
90   endgenerate // CR_BIT0_BIT7
91
92   assign er2CrTdiBit[8] = JTDI;
93
94// ------ Data Register 0 ------
95   assign er2Dr0_enable = (JCE2 & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000000)) ? 1'b1 : 1'b0;
96
97   assign tdo_er2Dr0 = er2Dr0TdiBit[0];
98
99   assign ip_functionality_id = 8'b00000001; //-- SPI Serial FLASH Programmer (0x01)
100
101// DR0_BIT0_BIT7
102   generate
103      for(i=0; i<=7; i=i+1)
104    begin:DR0_BIT0_BIT7
105       TYPEB BIT_N (.CLK (JTCK),
106            .RESET_N (JRSTN),
107            .CLKEN (er2Dr0_enable),
108            .TDI (er2Dr0TdiBit[i + 1]),
109            .TDO (er2Dr0TdiBit[i]),
110            .DATA_IN (ip_functionality_id[i]),
111            .CAPTURE_DR (captureDrER2));
112    end
113   endgenerate // DR0_BIT0_BIT7
114
115   assign er2Dr0TdiBit[8] = JTDI;
116
117// ------ Data Register 1 ------
118
119   assign er2Dr1_enable = (JCE2 & JSHIFT & SPIPROG_ENABLE & ~CONTROL_DATAN & (encodedDrSelBits == 8'b00000001)) ? 1'b1 : 1'b0;
120   
121   assign SPI_C = ~ (JTCK & er2Dr1_enable & spi_s);
122
123   assign SPI_D = JTDI & er2Dr1_enable;
124
125   // SPI_S_Proc
126   always @(negedge JTCK or negedge JRSTN)
127     begin
128    if (~JRSTN)
129          spi_s <= 1'b0;
130    else
131          if (JUPDATE)
132            spi_s <= 1'b0;
133          else
134            spi_s <= er2Dr1_enable;
135     end
136   
137   assign SPI_SN = ~spi_s;
138   
139   // SPI_Q_Proc
140   always @(negedge JTCK or negedge JRSTN)
141     begin
142    if (~JRSTN)
143          spi_q_dly <= 'b0;
144    else
145          if (er2Dr1_enable)
146            spi_q_dly <= {spi_q_dly[5:0],SPI_Q};
147     end
148   
149   assign tdo_er2Dr1 = spi_q_dly[6];
150   
151   // ------ JTDO2 MUX ------
152   
153   assign JTDO2 = CONTROL_DATAN ? tdo_er2Cr :
154      (encodedDrSelBits == 8'b00000000) ? tdo_er2Dr0 :
155      (encodedDrSelBits == 8'b00000001) ? tdo_er2Dr1 : 1'b0;
156   
157   assign captureDrER2 = ~JSHIFT & JCE2;
158   
159endmodule
160

Archive Download this file

Branches:
master



interactive