Hardware Design: SIE
Sign in or create your account | Project List | Help
Hardware Design: SIE Git Source Tree
Root/
| 1 | /*-- --------------------------------------------------------------------------- |
| 2 | -- |
| 3 | -- Name : TYPEA.v |
| 4 | -- |
| 5 | -- Description: |
| 6 | -- |
| 7 | -- This is one of the two types of cells that are used to create ER1/ER2 |
| 8 | -- register bits. |
| 9 | -- |
| 10 | -- $Log: typea.vhd,v $ |
| 11 | -- Revision 1.2 2002-11-13 18:33:59-08 jhsin |
| 12 | -- The SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 signals of the |
| 13 | -- dedicate logic JTAG_PORT didn't act as what their names implied. |
| 14 | -- The SHIFT_DR_CAPTURE_DR actually acts as SHIFT_DR. |
| 15 | -- The ENABLE_ER1/2 actually acts as SHIFT_DR_CAPTURE_DR. |
| 16 | -- These had caused a lot of headaches for a long time and now they are |
| 17 | -- fixed by: |
| 18 | -- (1) Use SHIFT_DR_CAPTURE_DR and ENABLE_ER1/2 to create |
| 19 | -- CAPTURE_DR for all typeA, typeB bits in the ER1, ER2 registers. |
| 20 | -- (2) Use ENABLE_ER1 or the enESR, enCSR, enBAR (these 3 signals |
| 21 | -- have the same waveform of ENABLE_ER2) directly to be the CLKEN |
| 22 | -- of all typeA, typeB bits in the ER1, ER2 registers. |
| 23 | -- (3) Modify typea.vhd to use only UPDATE_DR signal for the clock enable |
| 24 | -- of the holding flip-flop. |
| 25 | -- These changes caused ispTracy.vhd and cge.dat changes and the new |
| 26 | -- CGE.exe version will be 1.3.5. |
| 27 | -- |
| 28 | -- Revision 1.1 2002-05-01 18:13:51-07 jhsin |
| 29 | -- Added RCS version control header to file. No code changes. |
| 30 | -- |
| 31 | -- $Header: \\\\hqfile2\\ipcores\\rcs\\hqfile2\\ipcores\\rcswork\\isptracy\\VHDL\\Implementation\\typea.vhd,v 1.2 2002-11-13 18:33:59-08 jhsin Exp $ |
| 32 | -- |
| 33 | -- Copyright (C) 2002 Lattice Semiconductor Corp. All rights reserved. |
| 34 | -- |
| 35 | -- ---------------------------------------------------------------------------*/ |
| 36 | |
| 37 | module TYPEA( |
| 38 | input CLK, |
| 39 | input RESET_N, |
| 40 | input CLKEN, |
| 41 | input TDI, |
| 42 | output TDO, |
| 43 | output reg DATA_OUT, |
| 44 | input DATA_IN, |
| 45 | input CAPTURE_DR, |
| 46 | input UPDATE_DR |
| 47 | ); |
| 48 | |
| 49 | reg tdoInt; |
| 50 | |
| 51 | |
| 52 | always @ (negedge CLK or negedge RESET_N) |
| 53 | begin |
| 54 | if (RESET_N == 1'b0) |
| 55 | tdoInt <= 1'b0; |
| 56 | else if (CLK == 1'b0) |
| 57 | if (CLKEN == 1'b1) |
| 58 | if (CAPTURE_DR == 1'b0) |
| 59 | tdoInt <= TDI; |
| 60 | else |
| 61 | tdoInt <= DATA_IN; |
| 62 | end |
| 63 | |
| 64 | assign TDO = tdoInt; |
| 65 | |
| 66 | always @ (negedge CLK or negedge RESET_N) |
| 67 | begin |
| 68 | if (RESET_N == 1'b0) |
| 69 | DATA_OUT <= 1'b0; |
| 70 | else if (CLK == 1'b0) |
| 71 | if (UPDATE_DR == 1'b1) |
| 72 | DATA_OUT <= tdoInt; |
| 73 | end |
| 74 | endmodule |
| 75 |
Branches:
master
