Hardware Design: SIE
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| 1 | /*-- --------------------------------------------------------------------------- |
| 2 | -- |
| 3 | -- Name : TYPEB.vhd |
| 4 | -- |
| 5 | -- Description: |
| 6 | -- |
| 7 | -- This is one of the two types of cells that are used to create ER1/ER2 |
| 8 | -- register bits. |
| 9 | -- |
| 10 | -- $Log: typeb.vhd,v $ |
| 11 | -- Revision 1.2 2002-08-01 16:39:33-07 jhsin |
| 12 | -- Modified typeb module to remove redundant DATA_OUT port. |
| 13 | -- |
| 14 | -- Revision 1.1 2002-05-01 18:13:51-07 jhsin |
| 15 | -- Added RCS version control header to file. No code changes. |
| 16 | -- |
| 17 | -- $Header: \\\\hqfile2\\ipcores\\rcs\\hqfile2\\ipcores\\rcswork\\isptracy\\VHDL\\Implementation\\typeb.vhd,v 1.2 2002-08-01 16:39:33-07 jhsin Exp $ |
| 18 | -- |
| 19 | -- Copyright (C) 2002 Lattice Semiconductor Corp. All rights reserved. |
| 20 | -- |
| 21 | -- ---------------------------------------------------------------------------*/ |
| 22 | module TYPEB |
| 23 | ( |
| 24 | input CLK, |
| 25 | input RESET_N, |
| 26 | input CLKEN, |
| 27 | input TDI, |
| 28 | output TDO, |
| 29 | input DATA_IN, |
| 30 | input CAPTURE_DR |
| 31 | ); |
| 32 | |
| 33 | reg tdoInt; |
| 34 | |
| 35 | always @ (negedge CLK or negedge RESET_N) |
| 36 | begin |
| 37 | if (RESET_N== 1'b0) |
| 38 | tdoInt <= 1'b0; |
| 39 | else if (CLK == 1'b0) |
| 40 | if (CLKEN==1'b1) |
| 41 | if (CAPTURE_DR==1'b0) |
| 42 | tdoInt <= TDI; |
| 43 | else |
| 44 | tdoInt <= DATA_IN; |
| 45 | end |
| 46 | |
| 47 | assign TDO = tdoInt; |
| 48 | |
| 49 | endmodule |
| 50 | |
| 51 |
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