Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	//-----------------------------------------------------------------
2	// Wishbone BlockRAM
3	//-----------------------------------------------------------------
4
5	module wb_bram #(
6	parameter mem_file_name = "none",
7	parameter adr_width = 11
8	) (
9	input clk_i,
10	input rst_i,
11	//
12	input wb_stb_i,
13	input wb_cyc_i,
14	input wb_we_i,
15	output wb_ack_o,
16	input [31:0] wb_adr_i,
17	output reg [31:0] wb_dat_o,
18	input [31:0] wb_dat_i,
19	input [ 3:0] wb_sel_i
20	);
21
22	//-----------------------------------------------------------------
23	// Storage depth in 32 bit words
24	//-----------------------------------------------------------------
25	parameter word_width = adr_width - 2;
26	parameter word_depth = (1 << word_width);
27
28	//-----------------------------------------------------------------
29	//
30	//-----------------------------------------------------------------
31	reg [31:0] ram [0:word_depth-1]; // actual RAM
32	reg ack;
33	wire [word_width-1:0] adr;
34
35
36	assign adr = wb_adr_i[adr_width-1:2]; //
37	assign wb_ack_o = wb_stb_i & ack;
38
39	always @(posedge clk_i)
40	begin
41	if (wb_stb_i && wb_cyc_i)
42	begin
43	if (wb_we_i)
44	ram[ adr ] <= wb_dat_i;
45
46	wb_dat_o <= ram[ adr ];
47	ack <= ~ack;
48	end else
49	ack <= 0;
50
51	end
52
53	initial
54	begin
55	if (mem_file_name != "none")
56	begin
57	$readmemh(mem_file_name, ram);
58	end
59	end
60
61	endmodule
62
63

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