Root/lm32/logic/sakc/rtl/wb_conbus/wb_conbus_defines.v

1/////////////////////////////////////////////////////////////////////
2//// ////
3//// WISHBONE Connection ShareBus Definitions ////
4//// ////
5//// ////
6//// Author: Johny Chi ////
7//// chisuhua@yahoo.com.cn ////
8//// ////
9//// ////
10//// Downloaded from: http://www.opencores.org/cores/wb_conmax/ ////
11//// ////
12/////////////////////////////////////////////////////////////////////
13/// ////
14//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
15//// ////
16//// This source file may be used and distributed without ////
17//// restriction provided that this copyright statement is not ////
18//// removed from the file and that any derivative work contains ////
19//// the original copyright notice and the associated disclaimer. ////
20//// ////
21//// This source file is free software; you can redistribute it ////
22//// and/or modify it under the terms of the GNU Lesser General ////
23//// Public License as published by the Free Software Foundation; ////
24//// either version 2.1 of the License, or (at your option) any ////
25//// later version. ////
26//// ////
27//// This source is distributed in the hope that it will be ////
28//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
29//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
30//// PURPOSE. See the GNU Lesser General Public License for more ////
31//// details. ////
32//// ////
33//// You should have received a copy of the GNU Lesser General ////
34//// Public License along with this source; if not, download it ////
35//// from http://www.opencores.org/lgpl.shtml ////
36//// ////
37//////////////////////////////////////////////////////////////////////
38
39
40
41`timescale 1ns / 10ps
42
43

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