Root/lm32/logic/sakc/rtl/wb_conbus/wb_conbus_top.v

1/////////////////////////////////////////////////////////////////////
2//// ////
3//// WISHBONE Connection Bus Top Level ////
4//// ////
5//// ////
6//// Author: Johny Chi ////
7//// chisuhua@yahoo.com.cn ////
8//// ////
9//// ////
10//// ////
11/////////////////////////////////////////////////////////////////////
12//// ////
13//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
14//// ////
15//// This source file may be used and distributed without ////
16//// restriction provided that this copyright statement is not ////
17//// removed from the file and that any derivative work contains ////
18//// the original copyright notice and the associated disclaimer. ////
19//// ////
20//// This source file is free software; you can redistribute it ////
21//// and/or modify it under the terms of the GNU Lesser General ////
22//// Public License as published by the Free Software Foundation; ////
23//// either version 2.1 of the License, or (at your option) any ////
24//// later version. ////
25//// ////
26//// This source is distributed in the hope that it will be ////
27//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
28//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
29//// PURPOSE. See the GNU Lesser General Public License for more ////
30//// details. ////
31//// ////
32//// You should have received a copy of the GNU Lesser General ////
33//// Public License along with this source; if not, download it ////
34//// from http://www.opencores.org/lgpl.shtml ////
35//// ////
36//////////////////////////////////////////////////////////////////////
37//
38// Description
39// 1. Up to 8 masters and 8 slaves share bus Wishbone connection
40// 2. no priorty arbitor , 8 masters are processed in a round
41// robin way,
42// 3. if WB_USE_TRISTATE was defined, the share bus is a tristate
43// bus, and use less logic resource.
44// 4. wb_conbus was synthesis to XC2S100-5-PQ208 using synplify,
45// Max speed >60M , and 374 SLICE if using Multiplexor bus
46// or 150 SLICE if using tri-state bus.
47//
48`include "wb_conbus_defines.v"
49`define dw 32 // Data bus Width
50`define aw 32 // Address bus Width
51`define sw `dw / 8 // Number of Select Lines
52`define mbusw `aw + `sw + `dw +4 //address width + byte select width + dat width + cyc + we + stb +cab , input from master interface
53`define sbusw 3 // ack + err + rty, input from slave interface
54`define mselectw 8 // number of masters
55`define sselectw 8 // number of slavers
56
57//`define WB_USE_TRISTATE
58
59
60module wb_conbus_top #(
61    parameter s0_addr_w = 4 , // slave 0 address decode width -- bit 31 is always ignored!
62    parameter s0_addr = 4'h0, // slave 0 address
63    parameter s1_addr_w = 4 , // slave 1 address decode width -- bit 31 is always ignored!
64    parameter s1_addr = 4'h1, // slave 1 address
65    parameter s27_addr_w = 8 , // slave 2 to slave 7 address decode width -- bit 31 is always ignored!
66    parameter s2_addr = 8'h92, // slave 2 address
67    parameter s3_addr = 8'h93, // slave 3 address
68    parameter s4_addr = 8'h94, // slave 4 address
69    parameter s5_addr = 8'h95, // slave 5 address
70    parameter s6_addr = 8'h96, // slave 6 address
71    parameter s7_addr = 8'h97 // slave 7 address
72) (
73    clk_i, rst_i,
74
75    // Master 0 Interface
76    m0_dat_i, m0_dat_o, m0_adr_i, m0_sel_i, m0_we_i, m0_cyc_i,
77    m0_stb_i, m0_ack_o, m0_err_o, m0_rty_o, m0_cab_i,
78
79    // Master 1 Interface
80    m1_dat_i, m1_dat_o, m1_adr_i, m1_sel_i, m1_we_i, m1_cyc_i,
81    m1_stb_i, m1_ack_o, m1_err_o, m1_rty_o, m1_cab_i,
82
83    // Master 2 Interface
84    m2_dat_i, m2_dat_o, m2_adr_i, m2_sel_i, m2_we_i, m2_cyc_i,
85    m2_stb_i, m2_ack_o, m2_err_o, m2_rty_o, m2_cab_i,
86
87    // Master 3 Interface
88    m3_dat_i, m3_dat_o, m3_adr_i, m3_sel_i, m3_we_i, m3_cyc_i,
89    m3_stb_i, m3_ack_o, m3_err_o, m3_rty_o, m3_cab_i,
90
91    // Master 4 Interface
92    m4_dat_i, m4_dat_o, m4_adr_i, m4_sel_i, m4_we_i, m4_cyc_i,
93    m4_stb_i, m4_ack_o, m4_err_o, m4_rty_o, m4_cab_i,
94
95    // Master 5 Interface
96    m5_dat_i, m5_dat_o, m5_adr_i, m5_sel_i, m5_we_i, m5_cyc_i,
97    m5_stb_i, m5_ack_o, m5_err_o, m5_rty_o, m5_cab_i,
98
99    // Master 6 Interface
100    m6_dat_i, m6_dat_o, m6_adr_i, m6_sel_i, m6_we_i, m6_cyc_i,
101    m6_stb_i, m6_ack_o, m6_err_o, m6_rty_o, m6_cab_i,
102
103    // Master 7 Interface
104    m7_dat_i, m7_dat_o, m7_adr_i, m7_sel_i, m7_we_i, m7_cyc_i,
105    m7_stb_i, m7_ack_o, m7_err_o, m7_rty_o, m7_cab_i,
106
107    // Slave 0 Interface
108    s0_dat_i, s0_dat_o, s0_adr_o, s0_sel_o, s0_we_o, s0_cyc_o,
109    s0_stb_o, s0_ack_i, s0_err_i, s0_rty_i, s0_cab_o,
110
111    // Slave 1 Interface
112    s1_dat_i, s1_dat_o, s1_adr_o, s1_sel_o, s1_we_o, s1_cyc_o,
113    s1_stb_o, s1_ack_i, s1_err_i, s1_rty_i, s1_cab_o,
114
115    // Slave 2 Interface
116    s2_dat_i, s2_dat_o, s2_adr_o, s2_sel_o, s2_we_o, s2_cyc_o,
117    s2_stb_o, s2_ack_i, s2_err_i, s2_rty_i, s2_cab_o,
118
119    // Slave 3 Interface
120    s3_dat_i, s3_dat_o, s3_adr_o, s3_sel_o, s3_we_o, s3_cyc_o,
121    s3_stb_o, s3_ack_i, s3_err_i, s3_rty_i, s3_cab_o,
122
123    // Slave 4 Interface
124    s4_dat_i, s4_dat_o, s4_adr_o, s4_sel_o, s4_we_o, s4_cyc_o,
125    s4_stb_o, s4_ack_i, s4_err_i, s4_rty_i, s4_cab_o,
126
127    // Slave 5 Interface
128    s5_dat_i, s5_dat_o, s5_adr_o, s5_sel_o, s5_we_o, s5_cyc_o,
129    s5_stb_o, s5_ack_i, s5_err_i, s5_rty_i, s5_cab_o,
130
131    // Slave 6 Interface
132    s6_dat_i, s6_dat_o, s6_adr_o, s6_sel_o, s6_we_o, s6_cyc_o,
133    s6_stb_o, s6_ack_i, s6_err_i, s6_rty_i, s6_cab_o,
134
135    // Slave 7 Interface
136    s7_dat_i, s7_dat_o, s7_adr_o, s7_sel_o, s7_we_o, s7_cyc_o,
137    s7_stb_o, s7_ack_i, s7_err_i, s7_rty_i, s7_cab_o
138
139    );
140
141////////////////////////////////////////////////////////////////////
142//
143// Module Parameters
144//
145
146
147
148////////////////////////////////////////////////////////////////////
149//
150// Module IOs
151//
152
153input clk_i, rst_i;
154
155// Master 0 Interface
156input [`dw-1:0] m0_dat_i;
157output [`dw-1:0] m0_dat_o;
158input [`aw-1:0] m0_adr_i;
159input [`sw-1:0] m0_sel_i;
160input m0_we_i;
161input m0_cyc_i;
162input m0_stb_i;
163input m0_cab_i;
164output m0_ack_o;
165output m0_err_o;
166output m0_rty_o;
167
168// Master 1 Interface
169input [`dw-1:0] m1_dat_i;
170output [`dw-1:0] m1_dat_o;
171input [`aw-1:0] m1_adr_i;
172input [`sw-1:0] m1_sel_i;
173input m1_we_i;
174input m1_cyc_i;
175input m1_stb_i;
176input m1_cab_i;
177output m1_ack_o;
178output m1_err_o;
179output m1_rty_o;
180
181// Master 2 Interface
182input [`dw-1:0] m2_dat_i;
183output [`dw-1:0] m2_dat_o;
184input [`aw-1:0] m2_adr_i;
185input [`sw-1:0] m2_sel_i;
186input m2_we_i;
187input m2_cyc_i;
188input m2_stb_i;
189input m2_cab_i;
190output m2_ack_o;
191output m2_err_o;
192output m2_rty_o;
193
194// Master 3 Interface
195input [`dw-1:0] m3_dat_i;
196output [`dw-1:0] m3_dat_o;
197input [`aw-1:0] m3_adr_i;
198input [`sw-1:0] m3_sel_i;
199input m3_we_i;
200input m3_cyc_i;
201input m3_stb_i;
202input m3_cab_i;
203output m3_ack_o;
204output m3_err_o;
205output m3_rty_o;
206
207// Master 4 Interface
208input [`dw-1:0] m4_dat_i;
209output [`dw-1:0] m4_dat_o;
210input [`aw-1:0] m4_adr_i;
211input [`sw-1:0] m4_sel_i;
212input m4_we_i;
213input m4_cyc_i;
214input m4_stb_i;
215input m4_cab_i;
216output m4_ack_o;
217output m4_err_o;
218output m4_rty_o;
219
220// Master 5 Interface
221input [`dw-1:0] m5_dat_i;
222output [`dw-1:0] m5_dat_o;
223input [`aw-1:0] m5_adr_i;
224input [`sw-1:0] m5_sel_i;
225input m5_we_i;
226input m5_cyc_i;
227input m5_stb_i;
228input m5_cab_i;
229output m5_ack_o;
230output m5_err_o;
231output m5_rty_o;
232
233// Master 6 Interface
234input [`dw-1:0] m6_dat_i;
235output [`dw-1:0] m6_dat_o;
236input [`aw-1:0] m6_adr_i;
237input [`sw-1:0] m6_sel_i;
238input m6_we_i;
239input m6_cyc_i;
240input m6_stb_i;
241input m6_cab_i;
242output m6_ack_o;
243output m6_err_o;
244output m6_rty_o;
245
246// Master 7 Interface
247input [`dw-1:0] m7_dat_i;
248output [`dw-1:0] m7_dat_o;
249input [`aw-1:0] m7_adr_i;
250input [`sw-1:0] m7_sel_i;
251input m7_we_i;
252input m7_cyc_i;
253input m7_stb_i;
254input m7_cab_i;
255output m7_ack_o;
256output m7_err_o;
257output m7_rty_o;
258
259// Slave 0 Interface
260input [`dw-1:0] s0_dat_i;
261output [`dw-1:0] s0_dat_o;
262output [`aw-1:0] s0_adr_o;
263output [`sw-1:0] s0_sel_o;
264output s0_we_o;
265output s0_cyc_o;
266output s0_stb_o;
267output s0_cab_o;
268input s0_ack_i;
269input s0_err_i;
270input s0_rty_i;
271
272// Slave 1 Interface
273input [`dw-1:0] s1_dat_i;
274output [`dw-1:0] s1_dat_o;
275output [`aw-1:0] s1_adr_o;
276output [`sw-1:0] s1_sel_o;
277output s1_we_o;
278output s1_cyc_o;
279output s1_stb_o;
280output s1_cab_o;
281input s1_ack_i;
282input s1_err_i;
283input s1_rty_i;
284
285// Slave 2 Interface
286input [`dw-1:0] s2_dat_i;
287output [`dw-1:0] s2_dat_o;
288output [`aw-1:0] s2_adr_o;
289output [`sw-1:0] s2_sel_o;
290output s2_we_o;
291output s2_cyc_o;
292output s2_stb_o;
293output s2_cab_o;
294input s2_ack_i;
295input s2_err_i;
296input s2_rty_i;
297
298// Slave 3 Interface
299input [`dw-1:0] s3_dat_i;
300output [`dw-1:0] s3_dat_o;
301output [`aw-1:0] s3_adr_o;
302output [`sw-1:0] s3_sel_o;
303output s3_we_o;
304output s3_cyc_o;
305output s3_stb_o;
306output s3_cab_o;
307input s3_ack_i;
308input s3_err_i;
309input s3_rty_i;
310
311// Slave 4 Interface
312input [`dw-1:0] s4_dat_i;
313output [`dw-1:0] s4_dat_o;
314output [`aw-1:0] s4_adr_o;
315output [`sw-1:0] s4_sel_o;
316output s4_we_o;
317output s4_cyc_o;
318output s4_stb_o;
319output s4_cab_o;
320input s4_ack_i;
321input s4_err_i;
322input s4_rty_i;
323
324// Slave 5 Interface
325input [`dw-1:0] s5_dat_i;
326output [`dw-1:0] s5_dat_o;
327output [`aw-1:0] s5_adr_o;
328output [`sw-1:0] s5_sel_o;
329output s5_we_o;
330output s5_cyc_o;
331output s5_stb_o;
332output s5_cab_o;
333input s5_ack_i;
334input s5_err_i;
335input s5_rty_i;
336
337// Slave 6 Interface
338input [`dw-1:0] s6_dat_i;
339output [`dw-1:0] s6_dat_o;
340output [`aw-1:0] s6_adr_o;
341output [`sw-1:0] s6_sel_o;
342output s6_we_o;
343output s6_cyc_o;
344output s6_stb_o;
345output s6_cab_o;
346input s6_ack_i;
347input s6_err_i;
348input s6_rty_i;
349
350// Slave 7 Interface
351input [`dw-1:0] s7_dat_i;
352output [`dw-1:0] s7_dat_o;
353output [`aw-1:0] s7_adr_o;
354output [`sw-1:0] s7_sel_o;
355output s7_we_o;
356output s7_cyc_o;
357output s7_stb_o;
358output s7_cab_o;
359input s7_ack_i;
360input s7_err_i;
361input s7_rty_i;
362
363
364////////////////////////////////////////////////////////////////////
365//
366// Local wires
367//
368
369wire [`mselectw -1:0] i_gnt_arb;
370wire [2:0] gnt;
371reg [`sselectw -1:0] i_ssel_dec;
372`ifdef WB_USE_TRISTATE
373wire [`mbusw -1:0] i_bus_m;
374`else
375reg [`mbusw -1:0] i_bus_m; // internal share bus, master data and control to slave
376`endif
377wire [`dw -1:0] i_dat_s; // internal share bus , slave data to master
378wire [`sbusw -1:0] i_bus_s; // internal share bus , slave control to master
379
380
381
382////////////////////////////////////////////////////////////////////
383//
384// Master output Interfaces
385//
386
387// master0
388assign m0_dat_o = i_dat_s;
389assign {m0_ack_o, m0_err_o, m0_rty_o} = i_bus_s & {3{i_gnt_arb[0]}};
390
391// master1
392assign m1_dat_o = i_dat_s;
393assign {m1_ack_o, m1_err_o, m1_rty_o} = i_bus_s & {3{i_gnt_arb[1]}};
394
395// master2
396
397assign m2_dat_o = i_dat_s;
398assign {m2_ack_o, m2_err_o, m2_rty_o} = i_bus_s & {3{i_gnt_arb[2]}};
399
400// master3
401
402assign m3_dat_o = i_dat_s;
403assign {m3_ack_o, m3_err_o, m3_rty_o} = i_bus_s & {3{i_gnt_arb[3]}};
404
405// master4
406
407assign m4_dat_o = i_dat_s;
408assign {m4_ack_o, m4_err_o, m4_rty_o} = i_bus_s & {3{i_gnt_arb[4]}};
409
410// master5
411
412assign m5_dat_o = i_dat_s;
413assign {m5_ack_o, m5_err_o, m5_rty_o} = i_bus_s & {3{i_gnt_arb[5]}};
414
415// master6
416
417assign m6_dat_o = i_dat_s;
418assign {m6_ack_o, m6_err_o, m6_rty_o} = i_bus_s & {3{i_gnt_arb[6]}};
419
420// master7
421
422assign m7_dat_o = i_dat_s;
423assign {m7_ack_o, m7_err_o, m7_rty_o} = i_bus_s & {3{i_gnt_arb[7]}};
424
425
426assign i_bus_s = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | s6_ack_i | s7_ack_i ,
427                   s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | s6_err_i | s7_err_i ,
428                   s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | s6_rty_i | s7_rty_i };
429
430////////////////////////////////
431// Slave output interface
432//
433// slave0
434assign {s0_adr_o, s0_sel_o, s0_dat_o, s0_we_o, s0_cab_o,s0_cyc_o} = i_bus_m[`mbusw -1:1];
435assign s0_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[0]; // stb_o = cyc_i & stb_i & i_ssel_dec
436
437// slave1
438
439assign {s1_adr_o, s1_sel_o, s1_dat_o, s1_we_o, s1_cab_o, s1_cyc_o} = i_bus_m[`mbusw -1:1];
440assign s1_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[1];
441
442// slave2
443
444assign {s2_adr_o, s2_sel_o, s2_dat_o, s2_we_o, s2_cab_o, s2_cyc_o} = i_bus_m[`mbusw -1:1];
445assign s2_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[2];
446
447// slave3
448
449assign {s3_adr_o, s3_sel_o, s3_dat_o, s3_we_o, s3_cab_o, s3_cyc_o} = i_bus_m[`mbusw -1:1];
450assign s3_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[3];
451
452// slave4
453
454assign {s4_adr_o, s4_sel_o, s4_dat_o, s4_we_o, s4_cab_o, s4_cyc_o} = i_bus_m[`mbusw -1:1];
455assign s4_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[4];
456
457// slave5
458
459assign {s5_adr_o, s5_sel_o, s5_dat_o, s5_we_o, s5_cab_o, s5_cyc_o} = i_bus_m[`mbusw -1:1];
460assign s5_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[5];
461
462// slave6
463
464assign {s6_adr_o, s6_sel_o, s6_dat_o, s6_we_o, s6_cab_o, s6_cyc_o} = i_bus_m[`mbusw -1:1];
465assign s6_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[6];
466
467// slave7
468
469assign {s7_adr_o, s7_sel_o, s7_dat_o, s7_we_o, s7_cab_o, s7_cyc_o} = i_bus_m[`mbusw -1:1];
470assign s7_stb_o = i_bus_m[1] & i_bus_m[0] & i_ssel_dec[7];
471
472///////////////////////////////////////
473// Master and Slave input interface
474//
475
476`ifdef WB_USE_TRISTATE
477// input from master interface
478assign i_bus_m = i_gnt_arb[0] ? {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i, m0_stb_i} : 72'bz ;
479assign i_bus_m = i_gnt_arb[1] ? {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i,m1_cyc_i, m1_stb_i} : 72'bz ;
480assign i_bus_m = i_gnt_arb[2] ? {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i, m2_stb_i} : 72'bz ;
481assign i_bus_m = i_gnt_arb[3] ? {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i, m3_stb_i} : 72'bz ;
482assign i_bus_m = i_gnt_arb[4] ? {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i, m4_stb_i} : 72'bz ;
483assign i_bus_m = i_gnt_arb[5] ? {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i, m5_stb_i} : 72'bz ;
484assign i_bus_m = i_gnt_arb[6] ? {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i, m6_stb_i} : 72'bz ;
485assign i_bus_m = i_gnt_arb[7] ? {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i} : 72'bz ;
486// input from slave interface
487assign i_dat_s = i_ssel_dec[0] ? s0_dat_i: 32'bz;
488assign i_dat_s = i_ssel_dec[1] ? s1_dat_i: 32'bz;
489assign i_dat_s = i_ssel_dec[2] ? s2_dat_i: 32'bz;
490assign i_dat_s = i_ssel_dec[3] ? s3_dat_i: 32'bz;
491assign i_dat_s = i_ssel_dec[4] ? s4_dat_i: 32'bz;
492assign i_dat_s = i_ssel_dec[5] ? s5_dat_i: 32'bz;
493assign i_dat_s = i_ssel_dec[6] ? s6_dat_i: 32'bz;
494assign i_dat_s = i_ssel_dec[7] ? s7_dat_i: 32'bz;
495
496`else
497
498always @(gnt , m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i,
499        m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i,
500        m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i,
501        m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i,
502        m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i,
503        m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i,
504        m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i,
505        m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i)
506        case(gnt)
507            3'h0: i_bus_m = {m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
508            3'h1: i_bus_m = {m1_adr_i, m1_sel_i, m1_dat_i, m1_we_i, m1_cab_i, m1_cyc_i,m1_stb_i};
509            3'h2: i_bus_m = {m2_adr_i, m2_sel_i, m2_dat_i, m2_we_i, m2_cab_i, m2_cyc_i,m2_stb_i};
510            3'h3: i_bus_m = {m3_adr_i, m3_sel_i, m3_dat_i, m3_we_i, m3_cab_i, m3_cyc_i,m3_stb_i};
511            3'h4: i_bus_m = {m4_adr_i, m4_sel_i, m4_dat_i, m4_we_i, m4_cab_i, m4_cyc_i,m4_stb_i};
512            3'h5: i_bus_m = {m5_adr_i, m5_sel_i, m5_dat_i, m5_we_i, m5_cab_i, m5_cyc_i,m5_stb_i};
513            3'h6: i_bus_m = {m6_adr_i, m6_sel_i, m6_dat_i, m6_we_i, m6_cab_i, m6_cyc_i,m6_stb_i};
514            3'h7: i_bus_m = {m7_adr_i, m7_sel_i, m7_dat_i, m7_we_i, m7_cab_i, m7_cyc_i,m7_stb_i};
515            default:i_bus_m = 72'b0;//{m0_adr_i, m0_sel_i, m0_dat_i, m0_we_i, m0_cab_i, m0_cyc_i,m0_stb_i};
516endcase
517
518assign i_dat_s = i_ssel_dec[0] ? s0_dat_i :
519                  i_ssel_dec[1] ? s1_dat_i :
520                  i_ssel_dec[2] ? s2_dat_i :
521                  i_ssel_dec[3] ? s3_dat_i :
522                  i_ssel_dec[4] ? s4_dat_i :
523                  i_ssel_dec[5] ? s5_dat_i :
524                  i_ssel_dec[6] ? s6_dat_i :
525                  i_ssel_dec[7] ? s7_dat_i : {`dw{1'b0}};
526`endif
527//
528// arbitor
529//
530assign i_gnt_arb[0] = (gnt == 3'd0);
531assign i_gnt_arb[1] = (gnt == 3'd1);
532assign i_gnt_arb[2] = (gnt == 3'd2);
533assign i_gnt_arb[3] = (gnt == 3'd3);
534assign i_gnt_arb[4] = (gnt == 3'd4);
535assign i_gnt_arb[5] = (gnt == 3'd5);
536assign i_gnt_arb[6] = (gnt == 3'd6);
537assign i_gnt_arb[7] = (gnt == 3'd7);
538
539wb_conbus_arb wb_conbus_arb(
540    .clk(clk_i),
541    .rst(rst_i),
542    .req({ m7_cyc_i,
543        m6_cyc_i,
544        m5_cyc_i,
545        m4_cyc_i,
546        m3_cyc_i,
547        m2_cyc_i,
548        m1_cyc_i,
549        m0_cyc_i}),
550    .gnt(gnt)
551);
552
553//////////////////////////////////
554// address decode logic
555//
556wire [7:0] m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec;
557always @(gnt, m0_ssel_dec, m1_ssel_dec, m2_ssel_dec, m3_ssel_dec, m4_ssel_dec, m5_ssel_dec, m6_ssel_dec, m7_ssel_dec)
558    case(gnt)
559        3'h0: i_ssel_dec = m0_ssel_dec;
560        3'h1: i_ssel_dec = m1_ssel_dec;
561        3'h2: i_ssel_dec = m2_ssel_dec;
562        3'h3: i_ssel_dec = m3_ssel_dec;
563        3'h4: i_ssel_dec = m4_ssel_dec;
564        3'h5: i_ssel_dec = m5_ssel_dec;
565        3'h6: i_ssel_dec = m6_ssel_dec;
566        3'h7: i_ssel_dec = m7_ssel_dec;
567        default: i_ssel_dec = 7'b0;
568endcase
569//
570// decode all master address before arbitor for running faster
571//
572assign m0_ssel_dec[0] = (m0_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
573assign m0_ssel_dec[1] = (m0_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
574assign m0_ssel_dec[2] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
575assign m0_ssel_dec[3] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
576assign m0_ssel_dec[4] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
577assign m0_ssel_dec[5] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
578assign m0_ssel_dec[6] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
579assign m0_ssel_dec[7] = (m0_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
580
581assign m1_ssel_dec[0] = (m1_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
582assign m1_ssel_dec[1] = (m1_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
583assign m1_ssel_dec[2] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
584assign m1_ssel_dec[3] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
585assign m1_ssel_dec[4] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
586assign m1_ssel_dec[5] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
587assign m1_ssel_dec[6] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
588assign m1_ssel_dec[7] = (m1_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
589
590assign m2_ssel_dec[0] = (m2_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
591assign m2_ssel_dec[1] = (m2_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
592assign m2_ssel_dec[2] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
593assign m2_ssel_dec[3] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
594assign m2_ssel_dec[4] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
595assign m2_ssel_dec[5] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
596assign m2_ssel_dec[6] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
597assign m2_ssel_dec[7] = (m2_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
598
599assign m3_ssel_dec[0] = (m3_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
600assign m3_ssel_dec[1] = (m3_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
601assign m3_ssel_dec[2] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
602assign m3_ssel_dec[3] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
603assign m3_ssel_dec[4] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
604assign m3_ssel_dec[5] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
605assign m3_ssel_dec[6] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
606assign m3_ssel_dec[7] = (m3_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
607
608assign m4_ssel_dec[0] = (m4_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
609assign m4_ssel_dec[1] = (m4_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
610assign m4_ssel_dec[2] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
611assign m4_ssel_dec[3] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
612assign m4_ssel_dec[4] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
613assign m4_ssel_dec[5] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
614assign m4_ssel_dec[6] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
615assign m4_ssel_dec[7] = (m4_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
616
617assign m5_ssel_dec[0] = (m5_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
618assign m5_ssel_dec[1] = (m5_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
619assign m5_ssel_dec[2] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
620assign m5_ssel_dec[3] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
621assign m5_ssel_dec[4] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
622assign m5_ssel_dec[5] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
623assign m5_ssel_dec[6] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
624assign m5_ssel_dec[7] = (m5_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
625
626assign m6_ssel_dec[0] = (m6_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
627assign m6_ssel_dec[1] = (m6_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
628assign m6_ssel_dec[2] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
629assign m6_ssel_dec[3] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
630assign m6_ssel_dec[4] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
631assign m6_ssel_dec[5] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
632assign m6_ssel_dec[6] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
633assign m6_ssel_dec[7] = (m6_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
634
635assign m7_ssel_dec[0] = (m7_adr_i[`aw -2 : `aw -1 - s0_addr_w ] == s0_addr);
636assign m7_ssel_dec[1] = (m7_adr_i[`aw -2 : `aw -1 - s1_addr_w ] == s1_addr);
637assign m7_ssel_dec[2] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s2_addr);
638assign m7_ssel_dec[3] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s3_addr);
639assign m7_ssel_dec[4] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s4_addr);
640assign m7_ssel_dec[5] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s5_addr);
641assign m7_ssel_dec[6] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s6_addr);
642assign m7_ssel_dec[7] = (m7_adr_i[`aw -2 : `aw -1 - s27_addr_w ] == s7_addr);
643
644//assign i_ssel_dec[0] = (i_bus_m[`mbusw -1 : `mbusw - s0_addr_w ] == s0_addr);
645//assign i_ssel_dec[1] = (i_bus_m[`mbusw -1 : `mbusw - s1_addr_w ] == s1_addr);
646//assign i_ssel_dec[2] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s2_addr);
647//assign i_ssel_dec[3] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s3_addr);
648//assign i_ssel_dec[4] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s4_addr);
649//assign i_ssel_dec[5] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s5_addr);
650//assign i_ssel_dec[6] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s6_addr);
651//assign i_ssel_dec[7] = (i_bus_m[`mbusw -1 : `mbusw - s27_addr_w ] == s7_addr);
652
653
654endmodule
655
656

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