Root/lm32/logic/sakc/rtl/wb_ddr/ddr_init.v

1//----------------------------------------------------------------------------
2// Wishbone DDR Controller
3//
4// (c) Joerg Bornschein (<jb@capsec.org>)
5//----------------------------------------------------------------------------
6`include "ddr_include.v"
7
8module ddr_init
9#(
10    parameter wait200_init = 26
11) (
12    input clk,
13    input reset,
14    input pulse78,
15    output wait200,
16    output init_done,
17    //
18    output mngt_req,
19    input mngt_ack,
20    output [`CBA_RNG] mngt_cba // CMD, BA and ADDRESS
21);
22
23reg cmd_req_reg;
24reg [`CMD_RNG] cmd_cmd_reg;
25reg [ `BA_RNG] cmd_ba_reg;
26reg [ `A_RNG] cmd_a_reg;
27reg [7:0] cmd_idle_reg;
28
29//---------------------------------------------------------------------------
30// Initial 200us delay
31//---------------------------------------------------------------------------
32
33// `define WAIT200_INIT 26
34// `define WAIT200_INIT 1
35
36reg [4:0] wait200_counter;
37reg wait200_reg;
38
39always @(posedge clk)
40begin
41    if (reset) begin
42        wait200_reg <= 1;
43        wait200_counter <= wait200_init;
44    end else begin
45        if (wait200_counter == 0)
46            wait200_reg <= 0;
47
48        if (wait200_reg & pulse78)
49            wait200_counter <= wait200_counter - 1;
50    end
51end
52
53assign wait200 = wait200_reg;
54
55//----------------------------------------------------------------------------
56// DDR Initialization State Machine
57//----------------------------------------------------------------------------
58
59parameter s_wait200 = 0;
60parameter s_init1 = 1;
61parameter s_init2 = 2;
62parameter s_init3 = 3;
63parameter s_init4 = 4;
64parameter s_init5 = 5;
65parameter s_init6 = 6;
66parameter s_waitack = 7;
67parameter s_idle = 8;
68
69reg [3:0] state;
70reg init_done_reg;
71
72assign mngt_cba = {cmd_cmd_reg, cmd_ba_reg, cmd_a_reg};
73assign mngt_req = cmd_req_reg;
74assign mngt_pri_req = ~init_done_reg;
75assign init_done = init_done_reg;
76
77always @(posedge clk or posedge reset)
78begin
79    if (reset) begin
80        init_done_reg <= 0;
81        state <= s_wait200;
82        cmd_idle_reg <= 0;
83        cmd_req_reg <= 0;
84        cmd_cmd_reg <= 'b0;
85        cmd_ba_reg <= 'b0;
86        cmd_a_reg <= 'b0;
87    end else begin
88        case (state)
89            s_wait200: begin
90                if (~wait200_reg) begin
91                        state <= s_init1;
92                        cmd_req_reg <= 1;
93                        cmd_cmd_reg <= `DDR_CMD_PRE; // PRE ALL
94                        cmd_a_reg[10] <= 1'b1;
95                    end
96                end
97            s_init1: begin
98                    if (mngt_ack) begin
99                        state <= s_init2;
100                        cmd_req_reg <= 1;
101                        cmd_cmd_reg <= `DDR_CMD_MRS; // EMRS
102                        cmd_ba_reg <= 2'b01;
103                        cmd_a_reg <= `DDR_INIT_EMRS;
104                    end
105                end
106            s_init2: begin
107                    if (mngt_ack) begin
108                        state <= s_init3;
109                        cmd_req_reg <= 1;
110                        cmd_cmd_reg <= `DDR_CMD_MRS; // MRS
111                        cmd_ba_reg <= 2'b00;
112                        cmd_a_reg <= `DDR_INIT_MRS1;
113                    end
114                end
115            s_init3: begin
116                    if (mngt_ack) begin
117                        state <= s_init4;
118                        cmd_req_reg <= 1;
119                        cmd_cmd_reg <= `DDR_CMD_PRE; // PRE ALL
120                        cmd_a_reg[10] <= 1'b1;
121                    end
122                end
123            s_init4: begin
124                    if (mngt_ack) begin
125                        state <= s_init5;
126                        cmd_req_reg <= 1;
127                        cmd_cmd_reg <= `DDR_CMD_AR; // AR
128                    end
129                end
130            s_init5: begin
131                    if (mngt_ack) begin
132                        state <= s_init6;
133                        cmd_req_reg <= 1;
134                        cmd_cmd_reg <= `DDR_CMD_AR; // AR
135                    end
136                end
137            s_init6: begin
138                    if (mngt_ack) begin
139                        init_done_reg <= 1;
140                        state <= s_waitack;
141                        cmd_req_reg <= 1;
142                        cmd_cmd_reg <= `DDR_CMD_MRS; // MRS
143                        cmd_ba_reg <= 2'b00;
144                        cmd_a_reg <= `DDR_INIT_MRS2;
145                    end
146                end
147            s_waitack: begin
148                    if (mngt_ack) begin
149                        state <= s_idle;
150                        cmd_req_reg <= 0;
151                        cmd_cmd_reg <= 'b0;
152                        cmd_ba_reg <= 'b0;
153                        cmd_a_reg <= 'b0;
154                    end
155                end
156            s_idle: begin
157                end
158        endcase ///////////////////////////////////////// INIT STATE MACHINE ///
159    end
160end
161
162
163endmodule
164
165

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