Root/lm32/logic/sakc/rtl/wb_ddr/ddr_rpath.v

1//----------------------------------------------------------------------------
2// Wishbone DDR Controller
3//
4// (c) Joerg Bornschein (<jb@capsec.org>)
5//----------------------------------------------------------------------------
6
7`include "ddr_include.v"
8
9module ddr_rpath
10(
11    input clk,
12    input reset,
13    // sample activate
14    input sample,
15    // RDATA async fifo
16    input rfifo_clk,
17    output rfifo_empty,
18    output [`RFIFO_RNG] rfifo_dout,
19    input rfifo_next,
20    // DDR
21    input [ `DQ_RNG] ddr_dq,
22    input [`DQS_RNG] ddr_dqs
23);
24
25//----------------------------------------------------------------------------
26// RDATA async. fifo
27//----------------------------------------------------------------------------
28
29wire [`RFIFO_RNG] rfifo_din;
30wire rfifo_wr;
31wire rfifo_full;
32
33async_fifo #(
34    .DATA_WIDTH( `RFIFO_WIDTH ),
35    .ADDRESS_WIDTH( 4 )
36) rfifo (
37    .Data_out( rfifo_dout ),
38    .Empty_out( rfifo_empty ),
39    .ReadEn_in( rfifo_next ),
40    .RClk( rfifo_clk ),
41    //
42    .Data_in( rfifo_din ),
43    .WriteEn_in( rfifo_wr ),
44    .Full_out( rfifo_full ),
45    .WClk( ~clk ),
46    .Clear_in( reset )
47);
48
49
50//----------------------------------------------------------------------------
51// Clean up incoming 'sample' signal and generate sample_dq
52//----------------------------------------------------------------------------
53
54// anti-meta-state
55//reg sample180;
56//always @(negedge clk) sample180 <= sample;
57wire sample180 = sample;
58
59
60reg sample_dq; // authoritive sample flag (after cleanup)
61reg sample_dq_delayed; // write to rfifo?
62reg [3:0] sample_count; // make sure sample_dq is up exactly
63                              // BURSTLENGTH/2 cycles
64
65always @(posedge clk or posedge reset)
66begin
67    if (reset) begin
68        sample_dq <= 0;
69        sample_dq_delayed <= 0;
70        sample_count <= 0;
71    end else begin
72        sample_dq_delayed <= sample_dq;
73        if (sample_count == 0) begin
74            if (sample180) begin
75                sample_dq <= 1;
76                sample_count <= 1;
77            end
78        end else if (sample_count == 4) begin
79            sample_dq <= 0;
80            sample_count <= 0;
81        end else
82            sample_count <= sample_count + 1;
83            
84    end
85end
86
87//----------------------------------------------------------------------------
88// Sampe DQ and fill RFIFO
89//----------------------------------------------------------------------------
90reg [15:0] ddr_dq_low, ddr_dq_high;
91
92always @(negedge clk )
93begin
94    if (reset)
95        ddr_dq_low <= 'b0;
96    else
97        ddr_dq_low <= ddr_dq;
98end
99
100always @(posedge clk)
101begin
102    if (reset)
103        ddr_dq_high <= 'b0;
104    else
105        ddr_dq_high <= ddr_dq;
106end
107
108assign rfifo_wr = sample_dq_delayed;
109assign rfifo_din = { ddr_dq_high, ddr_dq_low };
110
111endmodule
112
113

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