Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1
2	//----------------------------------------------------------------------------
3	// Wishbone DDR Controller
4	//
5	// (c) Joerg Bornschein (<jb@capsec.org>)
6	//----------------------------------------------------------------------------
7
8	module dpram
9	#(
10	parameter adr_width = 9,
11	parameter dat_width = 36
12	) (
13	input clk,
14	// Port 0
15	input [adr_width-1:0] adr0,
16	input we0,
17	input [dat_width-1:0] din0,
18	output reg [dat_width-1:0] dout0,
19	// Port 1
20	input [adr_width-1:0] adr1,
21	input we1,
22	input [dat_width-1:0] din1,
23	output reg [dat_width-1:0] dout1
24	);
25
26	parameter depth = (1 << adr_width);
27
28	// actual ram
29	reg [dat_width-1:0] ram [0:depth-1];
30
31	//------------------------------------------------------------------
32	// Syncronous Dual Port RAM Access
33	//------------------------------------------------------------------
34	always @(posedge clk)
35	begin
36	// Frst port
37	if (we0)
38	ram[adr0] <= din0;
39
40	dout0 <= ram[adr0];
41	end
42
43
44	always @(posedge clk)
45	begin
46	// Second port
47	if (we1)
48	ram[adr1] <= din1;
49
50	dout1 <= ram[adr1];
51	end
52
53	//------------------------------------------------------------------
54	// Initialize content to Zero
55	//------------------------------------------------------------------
56	integer i;
57
58	initial
59	begin
60	for(i=0; i<depth; i=i+1)
61	ram[i] <= 'b0;
62	end
63
64	endmodule
65

Branches:
master