Hardware Design: SIE
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| 1 | //--------------------------------------------------------------------------- |
| 2 | // Wishbone General Pupose IO Component |
| 3 | // |
| 4 | // 0x00 |
| 5 | // 0x10 gpio_in (read-only) |
| 6 | // 0x14 gpio_out (read/write) |
| 7 | // 0x18 gpio_oe (read/write) |
| 8 | // |
| 9 | //--------------------------------------------------------------------------- |
| 10 | |
| 11 | module wb_gpio ( |
| 12 | input clk, |
| 13 | input reset, |
| 14 | // Wishbone interface |
| 15 | input wb_stb_i, |
| 16 | input wb_cyc_i, |
| 17 | output wb_ack_o, |
| 18 | input wb_we_i, |
| 19 | input [31:0] wb_adr_i, |
| 20 | input [3:0] wb_sel_i, |
| 21 | input [31:0] wb_dat_i, |
| 22 | output reg [31:0] wb_dat_o, |
| 23 | // |
| 24 | output intr, |
| 25 | // IO Wires |
| 26 | input [31:0] gpio_in, |
| 27 | output reg [31:0] gpio_out, |
| 28 | output reg [31:0] gpio_oe |
| 29 | ); |
| 30 | |
| 31 | //--------------------------------------------------------------------------- |
| 32 | // |
| 33 | //--------------------------------------------------------------------------- |
| 34 | |
| 35 | wire [31:0] gpiocr = 32'b0; |
| 36 | |
| 37 | // Wishbone |
| 38 | reg ack; |
| 39 | assign wb_ack_o = wb_stb_i & wb_cyc_i & ack; |
| 40 | |
| 41 | wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i; |
| 42 | wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i; |
| 43 | |
| 44 | always @(posedge clk) |
| 45 | begin |
| 46 | if (reset) begin |
| 47 | ack <= 0; |
| 48 | gpio_out <= 'b0; |
| 49 | end else begin |
| 50 | // Handle WISHBONE access |
| 51 | ack <= 0; |
| 52 | |
| 53 | if (wb_rd & ~ack) begin // read cycle |
| 54 | ack <= 1; |
| 55 | |
| 56 | case (wb_adr_i[7:0]) |
| 57 | 'h00: wb_dat_o <= gpiocr; |
| 58 | 'h10: wb_dat_o <= gpio_in; |
| 59 | 'h14: wb_dat_o <= gpio_out; |
| 60 | 'h18: wb_dat_o <= gpio_oe; |
| 61 | default: wb_dat_o <= 32'b0; |
| 62 | endcase |
| 63 | end else if (wb_wr & ~ack ) begin // write cycle |
| 64 | ack <= 1; |
| 65 | |
| 66 | case (wb_adr_i[7:0]) |
| 67 | 'h00: begin |
| 68 | end |
| 69 | 'h14: gpio_out <= wb_dat_i; |
| 70 | 'h18: gpio_oe <= wb_dat_i; |
| 71 | endcase |
| 72 | end |
| 73 | end |
| 74 | end |
| 75 | |
| 76 | |
| 77 | endmodule |
| 78 |
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