Root/lm32/logic/sakc/rtl/wb_sram/wb_sram16.v

1//----------------------------------------------------------------------------
2// Wishbone SRAM controller
3//----------------------------------------------------------------------------
4module wb_sram16 #(
5    parameter adr_width = 18,
6    parameter latency = 0 // 0 .. 7
7) (
8    input clk,
9    input reset,
10    // Wishbone interface
11    input wb_stb_i,
12    input wb_cyc_i,
13    output reg wb_ack_o,
14    input wb_we_i,
15    input [31:0] wb_adr_i,
16    input [3:0] wb_sel_i,
17    input [31:0] wb_dat_i,
18    output reg [31:0] wb_dat_o,
19    // SRAM connection
20    output reg [adr_width-1:0] sram_adr,
21    inout [15:0] sram_dat,
22    output reg [1:0] sram_be_n, // Byte Enable
23    output reg sram_ce_n, // Chip Enable
24    output reg sram_oe_n, // Output Enable
25    output reg sram_we_n // Write Enable
26);
27
28//----------------------------------------------------------------------------
29//
30//----------------------------------------------------------------------------
31
32// Wishbone handling
33wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
34wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
35
36// Translate wishbone address to sram address
37wire [adr_width-1:0] adr1 = { wb_adr_i[adr_width:2], 1'b0 };
38wire [adr_width-1:0] adr2 = { wb_adr_i[adr_width:2], 1'b1 };
39
40// Tri-State-Driver
41reg [15:0] wdat;
42reg wdat_oe;
43
44assign sram_dat = wdat_oe ? wdat : 16'bz;
45
46
47// Latency countdown
48reg [2:0] lcount;
49
50//----------------------------------------------------------------------------
51// State Machine
52//----------------------------------------------------------------------------
53parameter s_idle = 0;
54parameter s_read1 = 1;
55parameter s_read2 = 2;
56parameter s_write1 = 3;
57parameter s_write2 = 4;
58parameter s_write3 = 5;
59
60reg [2:0] state;
61
62always @(posedge clk)
63begin
64    if (reset) begin
65        state <= s_idle;
66        lcount <= 0;
67        wb_ack_o <= 0;
68    end else begin
69        case (state)
70        s_idle: begin
71            wb_ack_o <= 0;
72
73            if (wb_rd) begin
74                sram_ce_n <= 0;
75                sram_oe_n <= 0;
76                sram_we_n <= 1;
77                sram_adr <= adr1;
78                sram_be_n <= 2'b00;
79                wdat_oe <= 0;
80                lcount <= latency;
81                state <= s_read1;
82            end else if (wb_wr) begin
83                sram_ce_n <= 0;
84                sram_oe_n <= 1;
85                sram_we_n <= 0;
86                sram_adr <= adr1;
87                sram_be_n <= ~wb_sel_i[1:0];
88                wdat <= wb_dat_i[15:0];
89                wdat_oe <= 1;
90                lcount <= latency;
91                state <= s_write1;
92            end else begin
93                sram_ce_n <= 1;
94                sram_oe_n <= 1;
95                sram_we_n <= 1;
96            end
97        end
98        s_read1: begin
99            if (lcount != 0) begin
100                lcount <= lcount - 1;
101            end else begin
102                wb_dat_o[15:0] <= sram_dat;
103                sram_ce_n <= 0;
104                sram_oe_n <= 0;
105                sram_we_n <= 1;
106                sram_adr <= adr2;
107                sram_be_n <= 2'b00;
108                wdat_oe <= 0;
109                lcount <= latency;
110                state <= s_read2;
111            end
112        end
113        s_read2: begin
114            if (lcount != 0) begin
115                lcount <= lcount - 1;
116            end else begin
117                wb_dat_o[31:16] <= sram_dat;
118                wb_ack_o <= 1;
119                sram_ce_n <= 1;
120                sram_oe_n <= 1;
121                sram_we_n <= 1;
122                state <= s_idle;
123            end
124        end
125        s_write1: begin
126            if (lcount != 0) begin
127                lcount <= lcount - 1;
128            end else begin
129                sram_ce_n <= 0;
130                sram_oe_n <= 1;
131                sram_we_n <= 1;
132                state <= s_write2;
133            end
134        end
135        s_write2: begin
136                sram_ce_n <= 0;
137                sram_oe_n <= 1;
138                sram_we_n <= 0;
139                sram_adr <= adr2;
140                sram_be_n <= ~wb_sel_i[3:2];
141                wdat <= wb_dat_i[31:16];
142                wdat_oe <= 1;
143                lcount <= latency;
144                wb_ack_o <= 1;
145                state <= s_write3;
146        end
147        s_write3: begin
148            wb_ack_o <= 0;
149            if (lcount != 0) begin
150                lcount <= lcount - 1;
151            end else begin
152                sram_ce_n <= 1;
153                sram_oe_n <= 1;
154                sram_we_n <= 1;
155                wdat_oe <= 0;
156                state <= s_idle;
157            end
158        end
159        endcase
160    end
161end
162
163endmodule
164

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