Root/lm32/logic/sakc/rtl/wb_sram/wb_sram32.v

1//----------------------------------------------------------------------------
2// Wishbone SRAM controller
3//----------------------------------------------------------------------------
4module wb_sram32 #(
5    parameter adr_width = 18,
6    parameter latency = 0 // 0 .. 7
7) (
8    input clk,
9    input reset,
10    // Wishbone interface
11    input wb_stb_i,
12    input wb_cyc_i,
13    output reg wb_ack_o,
14    input wb_we_i,
15    input [31:0] wb_adr_i,
16    input [3:0] wb_sel_i,
17    input [31:0] wb_dat_i,
18    output reg [31:0] wb_dat_o,
19    // SRAM connection
20    output reg [adr_width-1:0] sram_adr,
21    inout [31:0] sram_dat,
22    output reg [3:0] sram_be_n, // Byte Enable
23    output reg sram_ce_n, // Chip Enable
24    output reg sram_oe_n, // Output Enable
25    output reg sram_we_n // Write Enable
26);
27
28//----------------------------------------------------------------------------
29//
30//----------------------------------------------------------------------------
31
32// Wishbone handling
33wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i & ~wb_ack_o;
34wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & ~wb_ack_o;
35
36// Translate wishbone address to sram address
37wire [adr_width-1:0] adr = wb_adr_i[adr_width+1:2];
38
39// Tri-State-Driver
40reg [31:0] wdat;
41reg wdat_oe;
42
43assign sram_dat = wdat_oe ? wdat : 32'bz;
44
45
46// Latency countdown
47reg [2:0] lcount;
48
49//----------------------------------------------------------------------------
50// State Machine
51//----------------------------------------------------------------------------
52parameter s_idle = 0;
53parameter s_read = 1;
54parameter s_write = 2;
55
56reg [2:0] state;
57
58always @(posedge clk)
59begin
60    if (reset) begin
61        state <= s_idle;
62        lcount <= 0;
63        wb_ack_o <= 0;
64    end else begin
65        case (state)
66        s_idle: begin
67            wb_ack_o <= 0;
68
69            if (wb_rd) begin
70                sram_ce_n <= 0;
71                sram_oe_n <= 0;
72                sram_we_n <= 1;
73                sram_adr <= adr;
74                sram_be_n <= 4'b0000;
75                wdat_oe <= 0;
76                lcount <= latency;
77                state <= s_read;
78            end else if (wb_wr) begin
79                sram_ce_n <= 0;
80                sram_oe_n <= 1;
81                sram_we_n <= 0;
82                sram_adr <= adr;
83                sram_be_n <= ~wb_sel_i;
84                wdat <= wb_dat_i;
85                wdat_oe <= 1;
86                lcount <= latency;
87                state <= s_write;
88            end else begin
89                sram_ce_n <= 1;
90                sram_oe_n <= 1;
91                sram_we_n <= 1;
92                wdat_oe <= 0;
93            end
94        end
95        s_read: begin
96            if (lcount != 0) begin
97                lcount <= lcount - 1;
98            end else begin
99                sram_ce_n <= 1;
100                sram_oe_n <= 1;
101                sram_we_n <= 1;
102                wb_dat_o <= sram_dat;
103                wb_ack_o <= 1;
104                state <= s_idle;
105            end
106        end
107        s_write: begin
108            if (lcount != 0) begin
109                lcount <= lcount - 1;
110            end else begin
111                sram_ce_n <= 1;
112                sram_oe_n <= 1;
113                sram_we_n <= 1;
114                wb_ack_o <= 1; // XXX We could acknoledge write XXX
115                state <= s_idle; // XXX requests 1 cycle ahead XXX
116            end
117        end
118        endcase
119    end
120end
121
122endmodule
123

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