Hardware Design: SIE
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| 1 | //--------------------------------------------------------------------------- |
| 2 | // Wishbone UART |
| 3 | // |
| 4 | // Register Description: |
| 5 | // |
| 6 | // 0x00 UCR [ 0 | 0 | 0 | tx_busy | 0 | 0 | rx_error | rx_avail ] |
| 7 | // 0x04 DATA |
| 8 | // |
| 9 | //--------------------------------------------------------------------------- |
| 10 | |
| 11 | module wb_uart #( |
| 12 | parameter clk_freq = 50000000, |
| 13 | parameter baud = 115200 |
| 14 | ) ( |
| 15 | input clk, |
| 16 | input reset, |
| 17 | // Wishbone interface |
| 18 | input wb_stb_i, |
| 19 | input wb_cyc_i, |
| 20 | output wb_ack_o, |
| 21 | input wb_we_i, |
| 22 | input [31:0] wb_adr_i, |
| 23 | input [3:0] wb_sel_i, |
| 24 | input [31:0] wb_dat_i, |
| 25 | output reg [31:0] wb_dat_o, |
| 26 | // Serial Wires |
| 27 | input uart_rxd, |
| 28 | output uart_txd |
| 29 | ); |
| 30 | |
| 31 | //--------------------------------------------------------------------------- |
| 32 | // Actual UART engine |
| 33 | //--------------------------------------------------------------------------- |
| 34 | wire [7:0] rx_data; |
| 35 | wire rx_avail; |
| 36 | wire rx_error; |
| 37 | reg rx_ack; |
| 38 | wire [7:0] tx_data; |
| 39 | reg tx_wr; |
| 40 | wire tx_busy; |
| 41 | |
| 42 | uart #( |
| 43 | .freq_hz( clk_freq ), |
| 44 | .baud( baud ) |
| 45 | ) uart0 ( |
| 46 | .clk( clk ), |
| 47 | .reset( reset ), |
| 48 | // |
| 49 | .uart_rxd( uart_rxd ), |
| 50 | .uart_txd( uart_txd ), |
| 51 | // |
| 52 | .rx_data( rx_data ), |
| 53 | .rx_avail( rx_avail ), |
| 54 | .rx_error( rx_error ), |
| 55 | .rx_ack( rx_ack ), |
| 56 | .tx_data( tx_data ), |
| 57 | .tx_wr( tx_wr ), |
| 58 | .tx_busy( tx_busy ) |
| 59 | ); |
| 60 | |
| 61 | //--------------------------------------------------------------------------- |
| 62 | // |
| 63 | //--------------------------------------------------------------------------- |
| 64 | wire [7:0] ucr = { 3'b0, tx_busy, 2'b0, rx_error, rx_avail }; |
| 65 | |
| 66 | wire wb_rd = wb_stb_i & wb_cyc_i & ~wb_we_i; |
| 67 | wire wb_wr = wb_stb_i & wb_cyc_i & wb_we_i & wb_sel_i[0]; |
| 68 | |
| 69 | reg ack; |
| 70 | |
| 71 | assign wb_ack_o = wb_stb_i & wb_cyc_i & ack; |
| 72 | |
| 73 | assign tx_data = wb_dat_i[7:0]; |
| 74 | |
| 75 | always @(posedge clk) |
| 76 | begin |
| 77 | if (reset) begin |
| 78 | wb_dat_o[31:8] <= 24'b0; |
| 79 | tx_wr <= 0; |
| 80 | rx_ack <= 0; |
| 81 | ack <= 0; |
| 82 | end else begin |
| 83 | wb_dat_o[31:8] <= 24'b0; |
| 84 | tx_wr <= 0; |
| 85 | rx_ack <= 0; |
| 86 | ack <= 0; |
| 87 | |
| 88 | if (wb_rd & ~ack) begin |
| 89 | ack <= 1; |
| 90 | |
| 91 | case (wb_adr_i[3:2]) |
| 92 | 2'b00: begin |
| 93 | wb_dat_o[7:0] <= ucr; |
| 94 | end |
| 95 | 2'b01: begin |
| 96 | wb_dat_o[7:0] <= rx_data; |
| 97 | rx_ack <= 1; |
| 98 | end |
| 99 | default: begin |
| 100 | wb_dat_o[7:0] <= 8'b0; |
| 101 | end |
| 102 | endcase |
| 103 | end else if (wb_wr & ~ack ) begin |
| 104 | ack <= 1; |
| 105 | |
| 106 | if ((wb_adr_i[3:2] == 2'b01) && ~tx_busy) begin |
| 107 | tx_wr <= 1; |
| 108 | end |
| 109 | end |
| 110 | end |
| 111 | end |
| 112 | |
| 113 | |
| 114 | endmodule |
| 115 |
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