Hardware Design: SIE
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| 1 | # ==== Clock inputs (CLK) ==== |
| 2 | NET "clk" LOC = "P38"; |
| 3 | NET "clk" PERIOD = 20 HIGH 50%; |
| 4 | NET led LOC = "P44"; |
| 5 | NET rst LOC = "P30"; |
| 6 | |
| 7 | # ==== UART ==== |
| 8 | NET "uart_rxd" LOC = "P68"; |
| 9 | NET "uart_txd" LOC = "P67"; |
| 10 | |
| 11 | #ADDRESS BUS |
| 12 | NET "addr<12>" LOC = "P90"; |
| 13 | NET "addr<11>" LOC = "P91"; |
| 14 | NET "addr<10>" LOC = "P85"; |
| 15 | NET "addr<9>" LOC = "P92"; |
| 16 | NET "addr<8>" LOC = "P94"; |
| 17 | NET "addr<7>" LOC = "P95"; |
| 18 | NET "addr<6>" LOC = "P98"; |
| 19 | NET "addr<5>" LOC = "P3"; |
| 20 | NET "addr<4>" LOC = "P2"; |
| 21 | NET "addr<3>" LOC = "P78"; |
| 22 | NET "addr<2>" LOC = "P79"; |
| 23 | NET "addr<1>" LOC = "P83"; |
| 24 | NET "addr<0>" LOC = "P84"; |
| 25 | |
| 26 | #DATA BUS |
| 27 | NET "sram_data<7>" LOC = "P4"; |
| 28 | NET "sram_data<6>" LOC = "P5"; |
| 29 | NET "sram_data<5>" LOC = "P9"; |
| 30 | NET "sram_data<4>" LOC = "P10"; |
| 31 | NET "sram_data<3>" LOC = "P11"; |
| 32 | NET "sram_data<2>" LOC = "P12"; |
| 33 | NET "sram_data<1>" LOC = "P15"; |
| 34 | NET "sram_data<0>" LOC = "P16"; |
| 35 | |
| 36 | #CONTROL BUS |
| 37 | |
| 38 | NET "nwe" LOC = "P88"; |
| 39 | NET "noe" LOC = "P86"; |
| 40 | NET "ncs" LOC = "P69"; |
| 41 |
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