Hardware Design: SIE

Hardware Design: SIE Git Source Tree

1	//---------------------------------------------------------------------------
2	//
3	// This file is used by ../rtl/lm32/* to configure CPU parameter
4	//
5	//---------------------------------------------------------------------------
6	`ifndef SYSTEM_CONF
7	`define SYSTEM_CONF
8	`define INCLUDE_LM32
9
10	//`timescale 1ns / 100 ps
11
12	`define CFG_EBA_RESET 32'h0
13	`define CFG_DEBA_RESET 32'h0
14
15	`define CFG_PL_MULTIPLY_ENABLED
16	`define CFG_PL_BARREL_SHIFT_ENABLED
17	`define CFG_SIGN_EXTEND_ENABLED
18	`define CFG_MC_DIVIDE_ENABLED
19
20	// Instruction Cache
21	// [0x00000000,0x80000000) cachable
22	// [0x80000000,0xffffffff] non-cachabel
23	`define CFG_ICACHE_ENABLED
24	`define CFG_ICACHE_ASSOCIATIVITY 1
25	`define CFG_ICACHE_SETS 512
26	`define CFG_ICACHE_BYTES_PER_LINE 16
27	`define CFG_ICACHE_BASE_ADDRESS 32'h0
28	`define CFG_ICACHE_LIMIT 32'h7fffffff
29
30	// Data Cache
31	// [0x00000000,0x80000000) cachable
32	// [0x80000000,0xffffffff] non-cachabel
33	// `define CFG_DCACHE_ENABLED
34	`define CFG_DCACHE_ASSOCIATIVITY 1
35	`define CFG_DCACHE_SETS 512
36	`define CFG_DCACHE_BYTES_PER_LINE 16
37	`define CFG_DCACHE_BASE_ADDRESS 32'h0
38	`define CFG_DCACHE_LIMIT 32'h7fffffff
39
40	// `define CFG_DEBUG_ENABLED
41	// `define CFG_ROM_DEBUG_ENABLED
42	// `define CFG_BREAKPOINTS 32'h1
43	// `define CFG_WATCHPOINTS 32'h1
44
45	`endif // SYSTEM_CONF
46

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