Hardware Design: SIE
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| 1 | //---------------------------------------------------------------------------- |
| 2 | // |
| 3 | //---------------------------------------------------------------------------- |
| 4 | `timescale 1 ns / 100 ps |
| 5 | |
| 6 | module system_tb; |
| 7 | |
| 8 | //---------------------------------------------------------------------------- |
| 9 | // Parameter (may differ for physical synthesis) |
| 10 | //---------------------------------------------------------------------------- |
| 11 | parameter tck = 20; // clock period in ns |
| 12 | parameter uart_baud_rate = 1152000; // uart baud rate for simulation |
| 13 | |
| 14 | parameter clk_freq = 1000000000 / tck; // Frequenzy in HZ |
| 15 | //---------------------------------------------------------------------------- |
| 16 | // |
| 17 | //---------------------------------------------------------------------------- |
| 18 | reg clk; |
| 19 | reg rst; |
| 20 | wire led; |
| 21 | |
| 22 | //---------------------------------------------------------------------------- |
| 23 | // UART STUFF (testbench uart, simulating a comm. partner) |
| 24 | //---------------------------------------------------------------------------- |
| 25 | wire uart_rxd; |
| 26 | wire uart_txd; |
| 27 | |
| 28 | //---------------------------------------------------------------------------- |
| 29 | // Device Under Test |
| 30 | //---------------------------------------------------------------------------- |
| 31 | system #( |
| 32 | .clk_freq( clk_freq ), |
| 33 | .uart_baud_rate( uart_baud_rate ) |
| 34 | ) dut ( |
| 35 | .clk( clk ), |
| 36 | // Debug |
| 37 | .rst( rst ), |
| 38 | .led( led ), |
| 39 | // Uart |
| 40 | .uart_rxd( uart_rxd ), |
| 41 | .uart_txd( uart_txd ) |
| 42 | ); |
| 43 | |
| 44 | /* Clocking device */ |
| 45 | initial clk <= 0; |
| 46 | always #(tck/2) clk <= ~clk; |
| 47 | |
| 48 | /* Simulation setup */ |
| 49 | initial begin |
| 50 | |
| 51 | |
| 52 | |
| 53 | $dumpfile("system_tb.vcd"); |
| 54 | //$monitor("%b,%b,%b,%b",clk,rst,uart_txd,uart_rxd); |
| 55 | //$dumpvars(-1, dut); |
| 56 | $dumpvars(-1,clk,rst,uart_txd); |
| 57 | // reset |
| 58 | #0 rst <= 0; |
| 59 | #80 rst <= 1; |
| 60 | |
| 61 | #(tck*10000) $finish; |
| 62 | end |
| 63 | |
| 64 | |
| 65 | |
| 66 | endmodule |
| 67 |
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