Hardware Design: SIE
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| 1 | /*-------------------------------------------------------------------- |
| 2 | * TITLE: Plasma DDR Initialization |
| 3 | * AUTHOR: Steve Rhoads (rhoadss@yahoo.com) |
| 4 | * DATE CREATED: 12/17/05 |
| 5 | * FILENAME: ddr_init.c |
| 6 | * PROJECT: Plasma CPU core |
| 7 | * COPYRIGHT: Software placed into the public domain by the author. |
| 8 | * Software 'as is' without warranty. Author liable for nothing. |
| 9 | * DESCRIPTION: |
| 10 | * Plasma DDR Initialization |
| 11 | * Supports 64MB (512Mb) MT46V32M16 by default. |
| 12 | * For 32 MB and 128 MB DDR parts change AddressLines and Bank shift: |
| 13 | * For 32 MB change 13->12 and 11->10. MT46V16M16 |
| 14 | * For 128 MB change 13->14 and 11->12. MT46V64M16 |
| 15 | *--------------------------------------------------------------------*/ |
| 16 | #define DDR_BASE 0x10000000 |
| 17 | #define MemoryRead(A) (*(volatile int*)(A)) |
| 18 | #define MemoryWrite(A,V) *(volatile int*)(A)=(V) |
| 19 | extern int putchar(int value); |
| 20 | extern int puts(const char *string); |
| 21 | extern void print_hex(unsigned long num); |
| 22 | |
| 23 | //SD_A <= address_reg(25 downto 13); --address row |
| 24 | //SD_BA <= address_reg(12 downto 11); --bank_address |
| 25 | //cmd := address_reg(6 downto 4); --bits RAS & CAS & WE |
| 26 | int DdrInitData[] = { |
| 27 | // AddressLines Bank Command |
| 28 | (0x000 << 13) | (0 << 11) | (7 << 4), //CKE=1; NOP="111" |
| 29 | (0x400 << 13) | (0 << 11) | (2 << 4), //A10=1; PRECHARGE ALL="010" |
| 30 | //#ifndef DLL_DISABLE |
| 31 | // (0x000 << 13) | (1 << 11) | (0 << 4), //enable DLL; BA="01"; LMR="000" |
| 32 | //#else |
| 33 | (0x001 << 13) | (1 << 11) | (0 << 4), //disable DLL; BA="01"; LMR="000" |
| 34 | //#endif |
| 35 | (0x121 << 13) | (0 << 11) | (0 << 4), //reset DLL, CL=2, BL=2; LMR="000" |
| 36 | (0x400 << 13) | (0 << 11) | (2 << 4), //A10=1; PRECHARGE ALL="010" |
| 37 | (0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001" |
| 38 | (0x000 << 13) | (0 << 11) | (1 << 4), //AUTO REFRESH="001 |
| 39 | (0x021 << 13) | (0 << 11) | (0 << 4) //clear DLL, CL=2, BL=2; LMR="000" |
| 40 | }; |
| 41 | |
| 42 | int DdrInit(void) |
| 43 | { |
| 44 | int i, j, k=0; |
| 45 | for(i = 0; i < sizeof(DdrInitData)/sizeof(int); ++i) |
| 46 | { |
| 47 | MemoryWrite(DDR_BASE + DdrInitData[i], 0); |
| 48 | for(j = 0; j < 4; ++j) |
| 49 | ++k; |
| 50 | } |
| 51 | for(j = 0; j < 100; ++j) |
| 52 | ++k; |
| 53 | k += MemoryRead(DDR_BASE); //Enable DDR |
| 54 | return k; |
| 55 | } |
| 56 | |
| 57 | #ifdef DDR_TEST_MAIN |
| 58 | int main() |
| 59 | { |
| 60 | volatile int *ptr = (int*)DDR_BASE; |
| 61 | int i; |
| 62 | |
| 63 | DdrInit(); |
| 64 | |
| 65 | ptr[0] = 0x12345678; |
| 66 | if(ptr[0] != 0x12345678) |
| 67 | putchar('X'); |
| 68 | for(i = 0; i < 10; ++i) |
| 69 | { |
| 70 | ptr[i] = i; |
| 71 | } |
| 72 | |
| 73 | for(i = 0; i < 10; ++i) |
| 74 | { |
| 75 | if(ptr[i] != i) |
| 76 | putchar('A' + i); |
| 77 | } |
| 78 | *(unsigned char*)DDR_BASE = 0x23; |
| 79 | *(unsigned char*)(DDR_BASE+1) = 0x45; |
| 80 | *(unsigned char*)(DDR_BASE+2) = 0x67; |
| 81 | *(unsigned char*)(DDR_BASE+3) = 0x89; |
| 82 | if(ptr[0] != 0x23456789) |
| 83 | putchar('Y'); |
| 84 | puts("\r\ndone\r\n"); |
| 85 | return 0; |
| 86 | } |
| 87 | #endif |
| 88 |
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