Root/plasma/logic/Makefile

1##########################################################
2### WARNING YOU MUST SET THE VARIABLE XILINX FIRST ##
3### /install_dir/Xilinx/10.1/ISE/
4##########################################################
5DESIGN = plasma
6PINS = $(DESIGN).ucf
7DEVICE = xc3s500e-VQ100-4
8BGFLAGS = -g TdoPin:PULLNONE -g DonePin:PULLUP \
9                  -g CRC:enable -g StartUpClk:CCLK
10
11SIM_CMD = /opt/cad/modeltech/bin/vsim
12SIM_COMP_SCRIPT = simulation/$(DESIGN)_TB.do
13SIMGEN_OPTIONS = -p $(FPGA_ARCH) -lang $(LANGUAGE)
14
15SIMTOP = $(DESIGN)_tb
16GHDL_SIM_OPT = --stop-time=1ms
17SIMDIR = simu
18GHDL_CMD = ghdl
19GHDL_SIMU_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
20GHDL_SYNTHESIS_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/unisim --warn-no-vital-generic
21GHDL_PANDR_FLAGS = --ieee=synopsys -P$$XILINX/ghdl/simprim --warn-no-vital-generic
22VIEW_CMD = gtkwave
23TESTBENCH_FILE = $(DESIGN)_TB.vhd
24SYNT_TESTBENCH_FILE = $(DESIGN)_TB_syn.vhd
25SYNTHESIS_FILE = simu/$(DESIGN)_synt.vhd
26LIBRARY_FILE = mlite_pack.vhd
27
28SRC_HDL = mlite_pack.vhd plasma.vhd ram_image.vhd alu.vhd control.vhd mem_ctrl.vhd mult.vhd shifter.vhd bus_mux.vhd mlite_cpu.vhd pc_next.vhd pipeline.vhd reg_bank.vhd uart.vhd
29 
30all: bits
31
32remake: clean-build all
33
34clean:
35    rm -rf *~ */*~ a.out *.log *.key *.edf *.ps trace.dat
36    rm -rf *.bit rm -rf simulation/work simulation/*wlf
37    rm -rf simulation/transcript
38
39clean-build:
40    rm -rf build
41
42cleanall: clean clean_ghdl
43    rm -rf build work $(DESIGN).bit
44
45bits: $(DESIGN).bit
46
47#
48# Synthesis
49#
50build/project.src:
51    @[ -d build ] || mkdir build
52    @rm -f $@
53    for i in $(SRC); do echo verilog work ../$$i >> $@; done
54    for i in $(SRC_HDL); do echo VHDL work ../$$i >> $@; done
55
56build/project.xst: build/project.src
57    echo "run" > $@
58    echo "-top $(DESIGN) " >> $@
59    echo "-p $(DEVICE)" >> $@
60    echo "-opt_mode Area" >> $@
61    echo "-opt_level 1" >> $@
62    echo "-ifn project.src" >> $@
63    echo "-ifmt mixed" >> $@
64    echo "-ofn project.ngc" >> $@
65    echo "-ofmt NGC" >> $@
66    echo "-rtlview yes" >> $@
67
68build/project.ngc: build/project.xst $(SRC)
69    cd build && xst -ifn project.xst -ofn project.log
70
71build/project.ngd: build/project.ngc $(PINS)
72    cd build && ngdbuild -p $(DEVICE) project.ngc -uc ../$(PINS)
73
74build/project.ncd: build/project.ngd
75    cd build && map -pr b -p $(DEVICE) project
76
77build/project_r.ncd: build/project.ncd
78    cd build && par -w project project_r.ncd
79
80build/project_r.twr: build/project_r.ncd
81    cd build && trce -v 25 project_r.ncd project.pcf
82
83$(DESIGN).bit: build/project_r.ncd build/project_r.twr
84    cd build && bitgen project_r.ncd -l -w $(BGFLAGS)
85    @mv -f build/project_r.bit $@
86
87build/project.vhd: build/project.ngc
88    cd build && netgen -w -ofmt vhdl project.ngc project.vhd
89
90sim:
91    cd simulation; $(SIM_CMD) -do $(DESIGN)_TB.do
92
93ghdl-simu : ghdl-compil ghdl-run ghdl-view
94
95ghdl-synthesis : ghdl-compil-synthesis ghdl-run ghdl-view
96
97ghdl-compil :
98    mkdir -p simu
99    $(GHDL_CMD) -i $(GHDL_SIMU_FLAGS) --workdir=simu --work=work $(TESTBENCH_FILE) $(LIBRARY_FILE) $(SRC_HDL)
100    $(GHDL_CMD) -m $(GHDL_SIMU_FLAGS) -fexplicit --workdir=simu --work=work $(SIMTOP)
101    @mv $(SIMTOP) simu/$(SIMTOP)
102
103ghdl-compil-synthesis: build/project.vhd
104    mkdir -p simu
105    cp build/project.vhd simu/$(DESIGN)_synt.vhd
106    $(GHDL_CMD) -i $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SYNT_TESTBENCH_FILE) $(SYNTHESIS_FILE)
107    $(GHDL_CMD) -m $(GHDL_SYNTHESIS_FLAGS) --workdir=simu --work=work $(SIMTOP)
108    @mv $(SIMTOP) simu/$(SIMTOP)
109
110ghdl-run :
111    @$(SIMDIR)/$(SIMTOP) $(GHDL_SIM_OPT) --vcdgz=$(SIMDIR)/$(SIMTOP).vcdgz
112
113ghdl-view:
114    gunzip --stdout $(SIMDIR)/$(SIMTOP).vcdgz | $(VIEW_CMD) --vcd
115
116clean_ghdl :
117    $(GHDL_CMD) --clean --workdir=simu
118    -rm -rf simu
119 
120

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