Root/plasma/logic/alu.vhd

1---------------------------------------------------------------------
2-- TITLE: Arithmetic Logic Unit
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 2/8/01
5-- FILENAME: alu.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- Implements the ALU.
11---------------------------------------------------------------------
12library ieee;
13use ieee.std_logic_1164.all;
14use work.mlite_pack.all;
15
16entity alu is
17   generic(alu_type : string := "DEFAULT");
18   port(a_in : in std_logic_vector(31 downto 0);
19        b_in : in std_logic_vector(31 downto 0);
20        alu_function : in alu_function_type;
21        c_alu : out std_logic_vector(31 downto 0));
22end; --alu
23
24architecture logic of alu is
25   signal do_add : std_logic;
26   signal sum : std_logic_vector(32 downto 0);
27   signal less_than : std_logic;
28begin
29
30   do_add <= '1' when alu_function = ALU_ADD else '0';
31   sum <= bv_adder(a_in, b_in, do_add);
32   less_than <= sum(32) when a_in(31) = b_in(31) or alu_function = ALU_LESS_THAN
33                else a_in(31);
34
35   GENERIC_ALU: if alu_type = "DEFAULT" generate
36      c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
37                                       alu_function=ALU_SUBTRACT else
38               ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
39                                alu_function=ALU_LESS_THAN_SIGNED else
40               a_in or b_in when alu_function=ALU_OR else
41               a_in and b_in when alu_function=ALU_AND else
42               a_in xor b_in when alu_function=ALU_XOR else
43               a_in nor b_in when alu_function=ALU_NOR else
44               ZERO;
45   end generate;
46
47   AREA_OPTIMIZED_ALU: if alu_type/="DEFAULT" generate
48      c_alu <= sum(31 downto 0) when alu_function=ALU_ADD or
49                                  alu_function=ALU_SUBTRACT else (others => 'Z');
50      c_alu <= ZERO(31 downto 1) & less_than when alu_function=ALU_LESS_THAN or
51                                  alu_function=ALU_LESS_THAN_SIGNED else
52                                          (others => 'Z');
53      c_alu <= a_in or b_in when alu_function=ALU_OR else (others => 'Z');
54      c_alu <= a_in and b_in when alu_function=ALU_AND else (others => 'Z');
55      c_alu <= a_in xor b_in when alu_function=ALU_XOR else (others => 'Z');
56      c_alu <= a_in nor b_in when alu_function=ALU_NOR else (others => 'Z');
57      c_alu <= ZERO when alu_function=ALU_NOTHING else (others => 'Z');
58   end generate;
59    
60end; --architecture logic
61
62

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