Root/plasma/logic/bus_mux.vhd

1---------------------------------------------------------------------
2-- TITLE: Bus Multiplexer / Signal Router
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 2/8/01
5-- FILENAME: bus_mux.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- This entity is the main signal router.
11-- It multiplexes signals from multiple sources to the correct location.
12-- The outputs are as follows:
13-- a_bus : goes to the ALU
14-- b_bus : goes to the ALU
15-- reg_dest_out : goes to the register bank
16-- take_branch : goes to pc_next
17---------------------------------------------------------------------
18library ieee;
19use ieee.std_logic_1164.all;
20use work.mlite_pack.all;
21
22entity bus_mux is
23   port(imm_in : in std_logic_vector(15 downto 0);
24        reg_source : in std_logic_vector(31 downto 0);
25        a_mux : in a_source_type;
26        a_out : out std_logic_vector(31 downto 0);
27
28        reg_target : in std_logic_vector(31 downto 0);
29        b_mux : in b_source_type;
30        b_out : out std_logic_vector(31 downto 0);
31
32        c_bus : in std_logic_vector(31 downto 0);
33        c_memory : in std_logic_vector(31 downto 0);
34        c_pc : in std_logic_vector(31 downto 2);
35        c_pc_plus4 : in std_logic_vector(31 downto 2);
36        c_mux : in c_source_type;
37        reg_dest_out : out std_logic_vector(31 downto 0);
38
39        branch_func : in branch_function_type;
40        take_branch : out std_logic);
41end; --entity bus_mux
42
43architecture logic of bus_mux is
44begin
45
46--Determine value of a_bus
47amux: process(reg_source, imm_in, a_mux, c_pc)
48begin
49   case a_mux is
50   when A_FROM_REG_SOURCE =>
51      a_out <= reg_source;
52   when A_FROM_IMM10_6 =>
53      a_out <= ZERO(31 downto 5) & imm_in(10 downto 6);
54   when A_FROM_PC =>
55      a_out <= c_pc & "00";
56   when others =>
57      a_out <= c_pc & "00";
58   end case;
59end process;
60
61--Determine value of b_bus
62bmux: process(reg_target, imm_in, b_mux)
63begin
64   case b_mux is
65   when B_FROM_REG_TARGET =>
66      b_out <= reg_target;
67   when B_FROM_IMM =>
68      b_out <= ZERO(31 downto 16) & imm_in;
69   when B_FROM_SIGNED_IMM =>
70      if imm_in(15) = '0' then
71         b_out(31 downto 16) <= ZERO(31 downto 16);
72      else
73         b_out(31 downto 16) <= "1111111111111111";
74      end if;
75      b_out(15 downto 0) <= imm_in;
76   when B_FROM_IMMX4 =>
77      if imm_in(15) = '0' then
78         b_out(31 downto 18) <= "00000000000000";
79      else
80         b_out(31 downto 18) <= "11111111111111";
81      end if;
82      b_out(17 downto 0) <= imm_in & "00";
83   when others =>
84      b_out <= reg_target;
85   end case;
86end process;
87
88--Determine value of c_bus
89cmux: process(c_bus, c_memory, c_pc, c_pc_plus4, imm_in, c_mux)
90begin
91   case c_mux is
92   when C_FROM_ALU => -- | C_FROM_SHIFT | C_FROM_MULT =>
93      reg_dest_out <= c_bus;
94   when C_FROM_MEMORY =>
95      reg_dest_out <= c_memory;
96   when C_FROM_PC =>
97      reg_dest_out <= c_pc(31 downto 2) & "00";
98   when C_FROM_PC_PLUS4 =>
99      reg_dest_out <= c_pc_plus4 & "00";
100   when C_FROM_IMM_SHIFT16 =>
101      reg_dest_out <= imm_in & ZERO(15 downto 0);
102   when others =>
103      reg_dest_out <= c_bus;
104   end case;
105end process;
106
107--Determine value of take_branch
108pc_mux: process(branch_func, reg_source, reg_target)
109   variable is_equal : std_logic;
110begin
111   if reg_source = reg_target then
112      is_equal := '1';
113   else
114      is_equal := '0';
115   end if;
116   case branch_func is
117   when BRANCH_LTZ =>
118      take_branch <= reg_source(31);
119   when BRANCH_LEZ =>
120      take_branch <= reg_source(31) or is_equal;
121   when BRANCH_EQ =>
122      take_branch <= is_equal;
123   when BRANCH_NE =>
124      take_branch <= not is_equal;
125   when BRANCH_GEZ =>
126      take_branch <= not reg_source(31);
127   when BRANCH_GTZ =>
128      take_branch <= not reg_source(31) and not is_equal;
129   when BRANCH_YES =>
130      take_branch <= '1';
131   when others =>
132      take_branch <= '0';
133   end case;
134end process;
135
136end; --architecture logic
137

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