Root/plasma/logic/mlite_pack.vhd

1---------------------------------------------------------------------
2-- TITLE: Plasma Misc. Package
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 2/15/01
5-- FILENAME: mlite_pack.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- Data types, constants, and add functions needed for the Plasma CPU.
11---------------------------------------------------------------------
12library ieee;
13use ieee.numeric_std.all;
14use ieee.std_logic_1164.all;
15
16
17package mlite_pack is
18   constant ZERO : std_logic_vector(31 downto 0) :=
19      "00000000000000000000000000000000";
20   constant ONES : std_logic_vector(31 downto 0) :=
21      "11111111111111111111111111111111";
22   --make HIGH_Z equal to ZERO if compiler complains
23   constant HIGH_Z : std_logic_vector(31 downto 0) :=
24      "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
25  
26   subtype alu_function_type is std_logic_vector(3 downto 0);
27   constant ALU_NOTHING : alu_function_type := "0000";
28   constant ALU_ADD : alu_function_type := "0001";
29   constant ALU_SUBTRACT : alu_function_type := "0010";
30   constant ALU_LESS_THAN : alu_function_type := "0011";
31   constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
32   constant ALU_OR : alu_function_type := "0101";
33   constant ALU_AND : alu_function_type := "0110";
34   constant ALU_XOR : alu_function_type := "0111";
35   constant ALU_NOR : alu_function_type := "1000";
36
37   subtype shift_function_type is std_logic_vector(1 downto 0);
38   constant SHIFT_NOTHING : shift_function_type := "00";
39   constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
40   constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
41   constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
42
43   subtype mult_function_type is std_logic_vector(3 downto 0);
44   constant MULT_NOTHING : mult_function_type := "0000";
45   constant MULT_READ_LO : mult_function_type := "0001";
46   constant MULT_READ_HI : mult_function_type := "0010";
47   constant MULT_WRITE_LO : mult_function_type := "0011";
48   constant MULT_WRITE_HI : mult_function_type := "0100";
49   constant MULT_MULT : mult_function_type := "0101";
50   constant MULT_SIGNED_MULT : mult_function_type := "0110";
51   constant MULT_DIVIDE : mult_function_type := "0111";
52   constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
53
54   subtype a_source_type is std_logic_vector(1 downto 0);
55   constant A_FROM_REG_SOURCE : a_source_type := "00";
56   constant A_FROM_IMM10_6 : a_source_type := "01";
57   constant A_FROM_PC : a_source_type := "10";
58
59   subtype b_source_type is std_logic_vector(1 downto 0);
60   constant B_FROM_REG_TARGET : b_source_type := "00";
61   constant B_FROM_IMM : b_source_type := "01";
62   constant B_FROM_SIGNED_IMM : b_source_type := "10";
63   constant B_FROM_IMMX4 : b_source_type := "11";
64
65   subtype c_source_type is std_logic_vector(2 downto 0);
66   constant C_FROM_NULL : c_source_type := "000";
67   constant C_FROM_ALU : c_source_type := "001";
68   constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
69   constant C_FROM_MULT : c_source_type := "001"; --same as alu
70   constant C_FROM_MEMORY : c_source_type := "010";
71   constant C_FROM_PC : c_source_type := "011";
72   constant C_FROM_PC_PLUS4 : c_source_type := "100";
73   constant C_FROM_IMM_SHIFT16: c_source_type := "101";
74   constant C_FROM_REG_SOURCEN: c_source_type := "110";
75
76   subtype pc_source_type is std_logic_vector(1 downto 0);
77   constant FROM_INC4 : pc_source_type := "00";
78   constant FROM_OPCODE25_0 : pc_source_type := "01";
79   constant FROM_BRANCH : pc_source_type := "10";
80   constant FROM_LBRANCH : pc_source_type := "11";
81
82   subtype branch_function_type is std_logic_vector(2 downto 0);
83   constant BRANCH_LTZ : branch_function_type := "000";
84   constant BRANCH_LEZ : branch_function_type := "001";
85   constant BRANCH_EQ : branch_function_type := "010";
86   constant BRANCH_NE : branch_function_type := "011";
87   constant BRANCH_GEZ : branch_function_type := "100";
88   constant BRANCH_GTZ : branch_function_type := "101";
89   constant BRANCH_YES : branch_function_type := "110";
90   constant BRANCH_NO : branch_function_type := "111";
91
92   -- mode(32=1,16=2,8=3), signed, write
93   subtype mem_source_type is std_logic_vector(3 downto 0);
94   constant MEM_FETCH : mem_source_type := "0000";
95   constant MEM_READ32 : mem_source_type := "0100";
96   constant MEM_WRITE32 : mem_source_type := "0101";
97   constant MEM_READ16 : mem_source_type := "1000";
98   constant MEM_READ16S : mem_source_type := "1010";
99   constant MEM_WRITE16 : mem_source_type := "1001";
100   constant MEM_READ8 : mem_source_type := "1100";
101   constant MEM_READ8S : mem_source_type := "1110";
102   constant MEM_WRITE8 : mem_source_type := "1101";
103
104   function bv_adder(a : in std_logic_vector;
105                     b : in std_logic_vector;
106                     do_add: in std_logic) return std_logic_vector;
107   function bv_negate(a : in std_logic_vector) return std_logic_vector;
108   function bv_increment(a : in std_logic_vector(31 downto 2)
109                         ) return std_logic_vector;
110   function bv_inc(a : in std_logic_vector
111                  ) return std_logic_vector;
112
113   -- For Altera
114   COMPONENT lpm_ram_dp
115      generic (
116         LPM_WIDTH : natural; -- MUST be greater than 0
117         LPM_WIDTHAD : natural; -- MUST be greater than 0
118         LPM_NUMWORDS : natural := 0;
119         LPM_INDATA : string := "REGISTERED";
120         LPM_OUTDATA : string := "REGISTERED";
121         LPM_RDADDRESS_CONTROL : string := "REGISTERED";
122         LPM_WRADDRESS_CONTROL : string := "REGISTERED";
123         LPM_FILE : string := "UNUSED";
124         LPM_TYPE : string := "LPM_RAM_DP";
125         USE_EAB : string := "OFF";
126         INTENDED_DEVICE_FAMILY : string := "UNUSED";
127         RDEN_USED : string := "TRUE";
128         LPM_HINT : string := "UNUSED");
129      port (
130         RDCLOCK : in std_logic := '0';
131         RDCLKEN : in std_logic := '1';
132         RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
133         RDEN : in std_logic := '1';
134         DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
135         WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
136         WREN : in std_logic;
137         WRCLOCK : in std_logic := '0';
138         WRCLKEN : in std_logic := '1';
139         Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
140   END COMPONENT;
141
142   -- For Altera
143   component LPM_RAM_DQ
144      generic (
145         LPM_WIDTH : natural; -- MUST be greater than 0
146         LPM_WIDTHAD : natural; -- MUST be greater than 0
147         LPM_NUMWORDS : natural := 0;
148         LPM_INDATA : string := "REGISTERED";
149         LPM_ADDRESS_CONTROL: string := "REGISTERED";
150         LPM_OUTDATA : string := "REGISTERED";
151         LPM_FILE : string := "UNUSED";
152         LPM_TYPE : string := "LPM_RAM_DQ";
153         USE_EAB : string := "OFF";
154         INTENDED_DEVICE_FAMILY : string := "UNUSED";
155         LPM_HINT : string := "UNUSED");
156        port (
157         DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
158         ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
159         INCLOCK : in std_logic := '0';
160         OUTCLOCK : in std_logic := '0';
161         WE : in std_logic;
162         Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
163   end component;
164
165   -- For Xilinx
166   component RAM16X1D
167      -- synthesis translate_off
168      generic (INIT : bit_vector := X"16");
169      -- synthesis translate_on
170      port (DPO : out STD_ULOGIC;
171            SPO : out STD_ULOGIC;
172            A0 : in STD_ULOGIC;
173            A1 : in STD_ULOGIC;
174            A2 : in STD_ULOGIC;
175            A3 : in STD_ULOGIC;
176            D : in STD_ULOGIC;
177            DPRA0 : in STD_ULOGIC;
178            DPRA1 : in STD_ULOGIC;
179            DPRA2 : in STD_ULOGIC;
180            DPRA3 : in STD_ULOGIC;
181            WCLK : in STD_ULOGIC;
182            WE : in STD_ULOGIC);
183   end component;
184
185   component pc_next
186      port(clk : in std_logic;
187           reset_in : in std_logic;
188           pc_new : in std_logic_vector(31 downto 2);
189           take_branch : in std_logic;
190           pause_in : in std_logic;
191           opcode25_0 : in std_logic_vector(25 downto 0);
192           pc_source : in pc_source_type;
193           pc_future : out std_logic_vector(31 downto 2);
194           pc_current : out std_logic_vector(31 downto 2);
195           pc_plus4 : out std_logic_vector(31 downto 2));
196   end component;
197
198   component mem_ctrl
199      port(clk : in std_logic;
200           reset_in : in std_logic;
201           pause_in : in std_logic;
202           nullify_op : in std_logic;
203           address_pc : in std_logic_vector(31 downto 2);
204           opcode_out : out std_logic_vector(31 downto 0);
205
206           address_in : in std_logic_vector(31 downto 0);
207           mem_source : in mem_source_type;
208           data_write : in std_logic_vector(31 downto 0);
209           data_read : out std_logic_vector(31 downto 0);
210           pause_out : out std_logic;
211
212           address_next : out std_logic_vector(31 downto 2);
213           byte_we_next : out std_logic_vector(3 downto 0);
214
215           address : out std_logic_vector(31 downto 2);
216           byte_we : out std_logic_vector(3 downto 0);
217           data_w : out std_logic_vector(31 downto 0);
218           data_r : in std_logic_vector(31 downto 0));
219   end component;
220
221   component control
222      port(opcode : in std_logic_vector(31 downto 0);
223           intr_signal : in std_logic;
224           rs_index : out std_logic_vector(5 downto 0);
225           rt_index : out std_logic_vector(5 downto 0);
226           rd_index : out std_logic_vector(5 downto 0);
227           imm_out : out std_logic_vector(15 downto 0);
228           alu_func : out alu_function_type;
229           shift_func : out shift_function_type;
230           mult_func : out mult_function_type;
231           branch_func : out branch_function_type;
232           a_source_out : out a_source_type;
233           b_source_out : out b_source_type;
234           c_source_out : out c_source_type;
235           pc_source_out: out pc_source_type;
236           mem_source_out:out mem_source_type;
237           exception_out: out std_logic);
238   end component;
239
240   component reg_bank
241      generic(memory_type : string := "XILINX_16X");
242      port(clk : in std_logic;
243           reset_in : in std_logic;
244           pause : in std_logic;
245           rs_index : in std_logic_vector(5 downto 0);
246           rt_index : in std_logic_vector(5 downto 0);
247           rd_index : in std_logic_vector(5 downto 0);
248           reg_source_out : out std_logic_vector(31 downto 0);
249           reg_target_out : out std_logic_vector(31 downto 0);
250           reg_dest_new : in std_logic_vector(31 downto 0);
251           intr_enable : out std_logic);
252   end component;
253
254   component bus_mux
255      port(imm_in : in std_logic_vector(15 downto 0);
256           reg_source : in std_logic_vector(31 downto 0);
257           a_mux : in a_source_type;
258           a_out : out std_logic_vector(31 downto 0);
259
260           reg_target : in std_logic_vector(31 downto 0);
261           b_mux : in b_source_type;
262           b_out : out std_logic_vector(31 downto 0);
263
264           c_bus : in std_logic_vector(31 downto 0);
265           c_memory : in std_logic_vector(31 downto 0);
266           c_pc : in std_logic_vector(31 downto 2);
267           c_pc_plus4 : in std_logic_vector(31 downto 2);
268           c_mux : in c_source_type;
269           reg_dest_out : out std_logic_vector(31 downto 0);
270
271           branch_func : in branch_function_type;
272           take_branch : out std_logic);
273   end component;
274
275   component alu
276      generic(alu_type : string := "DEFAULT");
277      port(a_in : in std_logic_vector(31 downto 0);
278           b_in : in std_logic_vector(31 downto 0);
279           alu_function : in alu_function_type;
280           c_alu : out std_logic_vector(31 downto 0));
281   end component;
282
283   component shifter
284      generic(shifter_type : string := "DEFAULT" );
285      port(value : in std_logic_vector(31 downto 0);
286           shift_amount : in std_logic_vector(4 downto 0);
287           shift_func : in shift_function_type;
288           c_shift : out std_logic_vector(31 downto 0));
289   end component;
290
291   component mult
292      generic(mult_type : string := "DEFAULT");
293      port(clk : in std_logic;
294           reset_in : in std_logic;
295           a, b : in std_logic_vector(31 downto 0);
296           mult_func : in mult_function_type;
297           c_mult : out std_logic_vector(31 downto 0);
298           pause_out : out std_logic);
299   end component;
300
301   component pipeline
302      port(clk : in std_logic;
303           reset : in std_logic;
304           a_bus : in std_logic_vector(31 downto 0);
305           a_busD : out std_logic_vector(31 downto 0);
306           b_bus : in std_logic_vector(31 downto 0);
307           b_busD : out std_logic_vector(31 downto 0);
308           alu_func : in alu_function_type;
309           alu_funcD : out alu_function_type;
310           shift_func : in shift_function_type;
311           shift_funcD : out shift_function_type;
312           mult_func : in mult_function_type;
313           mult_funcD : out mult_function_type;
314           reg_dest : in std_logic_vector(31 downto 0);
315           reg_destD : out std_logic_vector(31 downto 0);
316           rd_index : in std_logic_vector(5 downto 0);
317           rd_indexD : out std_logic_vector(5 downto 0);
318
319           rs_index : in std_logic_vector(5 downto 0);
320           rt_index : in std_logic_vector(5 downto 0);
321           pc_source : in pc_source_type;
322           mem_source : in mem_source_type;
323           a_source : in a_source_type;
324           b_source : in b_source_type;
325           c_source : in c_source_type;
326           c_bus : in std_logic_vector(31 downto 0);
327           pause_any : in std_logic;
328           pause_pipeline : out std_logic);
329   end component;
330
331   component mlite_cpu
332      generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
333              mult_type : string := "DEFAULT";
334              shifter_type : string := "DEFAULT";
335              alu_type : string := "DEFAULT";
336              pipeline_stages : natural := 2); --2 or 3
337      port(clk : in std_logic;
338           reset_in : in std_logic;
339           intr_in : in std_logic;
340
341           address_next : out std_logic_vector(31 downto 2); --for synch ram
342           byte_we_next : out std_logic_vector(3 downto 0);
343
344           address : out std_logic_vector(31 downto 2);
345           byte_we : out std_logic_vector(3 downto 0);
346           data_w : out std_logic_vector(31 downto 0);
347           data_r : in std_logic_vector(31 downto 0);
348           mem_pause : in std_logic);
349   end component;
350
351   component cache
352      generic(memory_type : string := "DEFAULT");
353      
354      port(clk : in std_logic;
355           reset : in std_logic;
356           address_next : in std_logic_vector(31 downto 2);
357           byte_we_next : in std_logic_vector(3 downto 0);
358           cpu_address : in std_logic_vector(31 downto 2);
359           mem_busy : in std_logic;
360
361           cache_check : out std_logic; --Stage1: address_next in first 2MB DDR
362           cache_checking : out std_logic; --Stage2: cache checking
363           cache_miss : out std_logic); --Stage2-3: cache miss
364   end component; --cache
365
366   component ram
367      generic(memory_type : string := "DEFAULT");
368      port(clk : in std_logic;
369           enable : in std_logic;
370           write_byte_enable : in std_logic_vector(3 downto 0);
371           address : in std_logic_vector(31 downto 2);
372           data_write : in std_logic_vector(31 downto 0);
373           data_read : out std_logic_vector(31 downto 0));
374   end component; --ram
375   
376   component uart
377      generic(log_file : string := "UNUSED");
378      port(clk : in std_logic;
379           reset : in std_logic;
380           cs : in std_logic;
381           nRdWr : in std_logic;
382           data_in : in std_logic_vector(7 downto 0);
383           data_out : out std_logic_vector(7 downto 0);
384           uart_read : in std_logic;
385           uart_write : out std_logic;
386           busy_write : out std_logic;
387           data_avail : out std_logic);
388   end component; --uart
389
390   component eth_dma
391      port(clk : in std_logic; --25 MHz
392           reset : in std_logic;
393           enable_eth : in std_logic;
394           select_eth : in std_logic;
395           rec_isr : out std_logic;
396           send_isr : out std_logic;
397
398           address : out std_logic_vector(31 downto 2); --to DDR
399           byte_we : out std_logic_vector(3 downto 0);
400           data_write : out std_logic_vector(31 downto 0);
401           data_read : in std_logic_vector(31 downto 0);
402           pause_in : in std_logic;
403
404           mem_address : in std_logic_vector(31 downto 2); --from CPU
405           mem_byte_we : in std_logic_vector(3 downto 0);
406           data_w : in std_logic_vector(31 downto 0);
407           pause_out : out std_logic;
408
409           E_RX_CLK : in std_logic; --2.5 MHz receive
410           E_RX_DV : in std_logic; --data valid
411           E_RXD : in std_logic_vector(3 downto 0); --receive nibble
412           E_TX_CLK : in std_logic; --2.5 MHz transmit
413           E_TX_EN : out std_logic; --transmit enable
414           E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
415   end component; --eth_dma
416
417   component plasma
418      generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
419              log_file : string := "UNUSED");
420      port(clk_in : in std_logic;
421           rst_in : in std_logic;
422           uart_write : out std_logic;
423           uart_read : in std_logic;
424   
425           addr : in std_logic_vector(12 downto 0);
426           sram_data : in std_logic_vector(7 downto 0);
427           nwe : in std_logic;
428           noe : in std_logic;
429           ncs : in std_logic;
430           irq_pin : out std_logic;
431           led : out std_logic);
432   end component; --plasma
433
434   component ddr_ctrl
435      port(clk : in std_logic;
436           clk_2x : in std_logic;
437           reset_in : in std_logic;
438
439           address : in std_logic_vector(25 downto 2);
440           byte_we : in std_logic_vector(3 downto 0);
441           data_w : in std_logic_vector(31 downto 0);
442           data_r : out std_logic_vector(31 downto 0);
443           active : in std_logic;
444           no_start : in std_logic;
445           no_stop : in std_logic;
446           pause : out std_logic;
447
448           SD_CK_P : out std_logic; --clock_positive
449           SD_CK_N : out std_logic; --clock_negative
450           SD_CKE : out std_logic; --clock_enable
451
452           SD_BA : out std_logic_vector(1 downto 0); --bank_address
453           SD_A : out std_logic_vector(12 downto 0); --address(row or col)
454           SD_CS : out std_logic; --chip_select
455           SD_RAS : out std_logic; --row_address_strobe
456           SD_CAS : out std_logic; --column_address_strobe
457           SD_WE : out std_logic; --write_enable
458
459           SD_DQ : inout std_logic_vector(15 downto 0); --data
460           SD_UDM : out std_logic; --upper_byte_enable
461           SD_UDQS : inout std_logic; --upper_data_strobe
462           SD_LDM : out std_logic; --low_byte_enable
463           SD_LDQS : inout std_logic); --low_data_strobe
464   end component; --ddr
465   
466end; --package mlite_pack
467
468
469package body mlite_pack is
470
471function bv_adder(a : in std_logic_vector;
472                  b : in std_logic_vector;
473                  do_add: in std_logic) return std_logic_vector is
474   variable carry_in : std_logic;
475   variable bb : std_logic_vector(a'length-1 downto 0);
476   variable result : std_logic_vector(a'length downto 0);
477begin
478   if do_add = '1' then
479      bb := b;
480      carry_in := '0';
481   else
482      bb := not b;
483      carry_in := '1';
484   end if;
485   for index in 0 to a'length-1 loop
486      result(index) := a(index) xor bb(index) xor carry_in;
487      carry_in := (carry_in and (a(index) or bb(index))) or
488                  (a(index) and bb(index));
489   end loop;
490   result(a'length) := carry_in xnor do_add;
491   return result;
492end; --function
493
494
495function bv_negate(a : in std_logic_vector) return std_logic_vector is
496   variable carry_in : std_logic;
497   variable not_a : std_logic_vector(a'length-1 downto 0);
498   variable result : std_logic_vector(a'length-1 downto 0);
499begin
500   not_a := not a;
501   carry_in := '1';
502   for index in a'reverse_range loop
503      result(index) := not_a(index) xor carry_in;
504      carry_in := carry_in and not_a(index);
505   end loop;
506   return result;
507end; --function
508
509
510function bv_increment(a : in std_logic_vector(31 downto 2)
511                     ) return std_logic_vector is
512   variable carry_in : std_logic;
513   variable result : std_logic_vector(31 downto 2);
514begin
515   carry_in := '1';
516   for index in 2 to 31 loop
517      result(index) := a(index) xor carry_in;
518      carry_in := a(index) and carry_in;
519   end loop;
520   return result;
521end; --function
522
523
524function bv_inc(a : in std_logic_vector
525                ) return std_logic_vector is
526   variable carry_in : std_logic;
527   variable result : std_logic_vector(a'length-1 downto 0);
528begin
529   carry_in := '1';
530   for index in 0 to a'length-1 loop
531      result(index) := a(index) xor carry_in;
532      carry_in := a(index) and carry_in;
533   end loop;
534   return result;
535end; --function
536
537end; --package body
538
539
540

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