Root/plasma/logic/pipeline.vhd

1---------------------------------------------------------------------
2-- TITLE: Pipeline
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 6/24/02
5-- FILENAME: pipeline.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- Controls the three stage pipeline by delaying the signals:
11-- a_bus, b_bus, alu/shift/mult_func, c_source, and rs_index.
12---------------------------------------------------------------------
13library ieee;
14use ieee.std_logic_1164.all;
15use work.mlite_pack.all;
16
17--Note: sigD <= sig after rising_edge(clk)
18entity pipeline is
19   port(clk : in std_logic;
20        reset : in std_logic;
21        a_bus : in std_logic_vector(31 downto 0);
22        a_busD : out std_logic_vector(31 downto 0);
23        b_bus : in std_logic_vector(31 downto 0);
24        b_busD : out std_logic_vector(31 downto 0);
25        alu_func : in alu_function_type;
26        alu_funcD : out alu_function_type;
27        shift_func : in shift_function_type;
28        shift_funcD : out shift_function_type;
29        mult_func : in mult_function_type;
30        mult_funcD : out mult_function_type;
31        reg_dest : in std_logic_vector(31 downto 0);
32        reg_destD : out std_logic_vector(31 downto 0);
33        rd_index : in std_logic_vector(5 downto 0);
34        rd_indexD : out std_logic_vector(5 downto 0);
35
36        rs_index : in std_logic_vector(5 downto 0);
37        rt_index : in std_logic_vector(5 downto 0);
38        pc_source : in pc_source_type;
39        mem_source : in mem_source_type;
40        a_source : in a_source_type;
41        b_source : in b_source_type;
42        c_source : in c_source_type;
43        c_bus : in std_logic_vector(31 downto 0);
44        pause_any : in std_logic;
45        pause_pipeline : out std_logic);
46end; --entity pipeline
47
48architecture logic of pipeline is
49   signal rd_index_reg : std_logic_vector(5 downto 0);
50   signal reg_dest_reg : std_logic_vector(31 downto 0);
51   signal reg_dest_delay : std_logic_vector(31 downto 0);
52   signal c_source_reg : c_source_type;
53   signal pause_enable_reg : std_logic;
54begin
55
56--When operating in three stage pipeline mode, the following signals
57--are delayed by one clock cycle: a_bus, b_bus, alu/shift/mult_func,
58--c_source, and rd_index.
59pipeline3: process(clk, reset, a_bus, b_bus, alu_func, shift_func, mult_func,
60      rd_index, rd_index_reg, pause_any, pause_enable_reg,
61      rs_index, rt_index,
62      pc_source, mem_source, a_source, b_source, c_source, c_source_reg,
63      reg_dest, reg_dest_reg, reg_dest_delay, c_bus)
64   variable pause_mult_clock : std_logic;
65   variable freeze_pipeline : std_logic;
66begin
67   if (pc_source /= FROM_INC4 and pc_source /= FROM_OPCODE25_0) or
68         mem_source /= MEM_FETCH or
69         (mult_func = MULT_READ_LO or mult_func = MULT_READ_HI) then
70      pause_mult_clock := '1';
71   else
72      pause_mult_clock := '0';
73   end if;
74
75   freeze_pipeline := not (pause_mult_clock and pause_enable_reg) and pause_any;
76   pause_pipeline <= pause_mult_clock and pause_enable_reg;
77   rd_indexD <= rd_index_reg;
78
79   -- The value written back into the register bank, signal reg_dest is tricky.
80   -- If reg_dest comes from the ALU via the signal c_bus, it is already delayed
81   -- into stage #3, because a_busD and b_busD are delayed. If reg_dest comes from
82   -- c_memory, pc_current, or pc_plus4 then reg_dest hasn't yet been delayed into
83   -- stage #3.
84   -- Instead of delaying c_memory, pc_current, and pc_plus4, these signals
85   -- are multiplexed into reg_dest which is then delayed. The decision to use
86   -- the already delayed c_bus or the delayed value of reg_dest (reg_dest_reg) is
87   -- based on a delayed value of c_source (c_source_reg).
88   
89   if c_source_reg = C_FROM_ALU then
90      reg_dest_delay <= c_bus; --delayed by 1 clock cycle via a_busD & b_busD
91   else
92      reg_dest_delay <= reg_dest_reg; --need to delay 1 clock cycle from reg_dest
93   end if;
94   reg_destD <= reg_dest_delay;
95
96   if reset = '1' then
97      a_busD <= ZERO;
98      b_busD <= ZERO;
99      alu_funcD <= ALU_NOTHING;
100      shift_funcD <= SHIFT_NOTHING;
101      mult_funcD <= MULT_NOTHING;
102      reg_dest_reg <= ZERO;
103      c_source_reg <= "000";
104      rd_index_reg <= "000000";
105      pause_enable_reg <= '0';
106   elsif rising_edge(clk) then
107      if freeze_pipeline = '0' then
108         if (rs_index = "000000" or rs_index /= rd_index_reg) or
109            (a_source /= A_FROM_REG_SOURCE or pause_enable_reg = '0') then
110            a_busD <= a_bus;
111         else
112            a_busD <= reg_dest_delay; --rs from previous operation (bypass stage)
113         end if;
114
115         if (rt_index = "000000" or rt_index /= rd_index_reg) or
116               (b_source /= B_FROM_REG_TARGET or pause_enable_reg = '0') then
117            b_busD <= b_bus;
118         else
119            b_busD <= reg_dest_delay; --rt from previous operation
120         end if;
121
122         alu_funcD <= alu_func;
123         shift_funcD <= shift_func;
124         mult_funcD <= mult_func;
125         reg_dest_reg <= reg_dest;
126         c_source_reg <= c_source;
127         rd_index_reg <= rd_index;
128      end if;
129
130      if pause_enable_reg = '0' and pause_any = '0' then
131         pause_enable_reg <= '1'; --enable pause_pipeline
132      elsif pause_mult_clock = '1' then
133         pause_enable_reg <= '0'; --disable pause_pipeline
134      end if;
135   end if;
136
137end process; --pipeline3
138
139end; --logic
140

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