Root/plasma/logic/plasma_TB.vhd

1---------------------------------------------------------------------
2-- TITLE: Test Bench
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 4/21/01
5-- FILENAME: tbench.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- This entity provides a test bench for testing the Plasma CPU core.
11---------------------------------------------------------------------
12library ieee;
13use ieee.std_logic_1164.all;
14--use work.mlite_pack.all;
15use ieee.std_logic_unsigned.all;
16
17entity plasma_tb is
18end; --entity tbench
19
20architecture logic of plasma_tb is
21   constant memory_type : string := "TRI_PORT_X";
22
23   signal clk_in : std_logic := '1';
24   signal rst_in : std_logic := '0';
25   signal addr : std_logic_vector(12 downto 0);
26   signal sram_data : std_logic_vector(7 downto 0);
27   signal nwe : std_logic;
28   signal noe : std_logic;
29   signal ncs : std_logic;
30   signal irq_pin : std_logic;
31   signal led : std_logic;
32   signal TxD : std_logic;
33   signal RxD : std_logic;
34
35   component plasma
36      generic(memory_type : string := "XILINX_X16"; log_file : string := "UNUSED");
37      port(clk_in : in std_logic;
38           rst_in : in std_logic;
39           uart_write : out std_logic;
40           uart_read : in std_logic;
41   
42           addr : in std_logic_vector(12 downto 0);
43           sram_data : in std_logic_vector(7 downto 0);
44           nwe : in std_logic;
45           noe : in std_logic;
46           ncs : in std_logic;
47           irq_pin : out std_logic;
48           led : out std_logic);
49   end component; --plasma
50
51begin --architecture
52   clk_in <= not clk_in after 50 ns;
53   rst_in <= '1' after 500 ns;
54   RxD <= '1';
55
56
57   u1_plasma: plasma
58      generic map (memory_type => memory_type, log_file => "UNUSED")
59      PORT MAP (
60         clk_in => clk_in,
61         rst_in => rst_in,
62         uart_read => RxD,
63         uart_write => TxD,
64         addr => addr,
65         sram_data => sram_data,
66         nwe => nwe,
67         noe => noe,
68         ncs => ncs,
69         irq_pin => irq_pin,
70         led => led
71     );
72
73end; --architecture logic
74

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