Root/plasma/logic/plasma_TB_syn.vhd

1---------------------------------------------------------------------
2-- TITLE: Test Bench
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 4/21/01
5-- FILENAME: tbench.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- This entity provides a test bench for testing the Plasma CPU core.
11---------------------------------------------------------------------
12library ieee;
13use ieee.std_logic_1164.all;
14use ieee.std_logic_unsigned.all;
15
16entity plasma_tb is
17end; --entity tbench
18
19architecture logic of plasma_tb is
20   constant memory_type : string := "TRI_PORT_X";
21
22   signal clk_in : std_logic := '1';
23   signal rst_in : std_logic := '0';
24   signal addr : std_logic_vector(12 downto 0);
25   signal sram_data : std_logic_vector(7 downto 0);
26   signal nwe : std_logic;
27   signal noe : std_logic;
28   signal ncs : std_logic;
29   signal irq_pin : std_logic;
30   signal led : std_logic;
31   signal TxD : std_logic;
32   signal RxD : std_logic;
33
34   component plasma
35      port(clk_in : in std_logic;
36           rst_in : in std_logic;
37           uart_write : out std_logic;
38           uart_read : in std_logic;
39   
40           addr : in std_logic_vector(12 downto 0);
41           sram_data : in std_logic_vector(7 downto 0);
42           nwe : in std_logic;
43           noe : in std_logic;
44           ncs : in std_logic;
45           irq_pin : out std_logic;
46           led : out std_logic);
47   end component; --plasma
48
49begin --architecture
50   clk_in <= not clk_in after 50 ns;
51   rst_in <= '1' after 500 ns;
52   RxD <= '1';
53
54
55   u1_plasma: plasma
56      PORT MAP (
57         clk_in => clk_in,
58         rst_in => rst_in,
59         uart_read => RxD,
60         uart_write => TxD,
61         addr => addr,
62         sram_data => sram_data,
63         nwe => nwe,
64         noe => noe,
65         ncs => ncs,
66         irq_pin => irq_pin,
67         led => led
68     );
69
70end; --architecture logic
71

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