Root/plasma/logic/ram.vhd

1---------------------------------------------------------------------
2-- TITLE: Random Access Memory
3-- AUTHOR: Steve Rhoads (rhoadss@yahoo.com)
4-- DATE CREATED: 4/21/01
5-- FILENAME: ram.vhd
6-- PROJECT: Plasma CPU core
7-- COPYRIGHT: Software placed into the public domain by the author.
8-- Software 'as is' without warranty. Author liable for nothing.
9-- DESCRIPTION:
10-- Implements the RAM, reads the executable from either "code.txt",
11-- or for Altera "code[0-3].hex".
12-- Modified from "The Designer's Guide to VHDL" by Peter J. Ashenden
13---------------------------------------------------------------------
14library ieee;
15use ieee.std_logic_1164.all;
16use ieee.std_logic_misc.all;
17use ieee.std_logic_arith.all;
18use ieee.std_logic_unsigned.all;
19use ieee.std_logic_textio.all;
20use std.textio.all;
21use work.mlite_pack.all;
22
23entity ram is
24   generic(memory_type : string := "DEFAULT");
25   port(clk : in std_logic;
26        enable : in std_logic;
27        write_byte_enable : in std_logic_vector(3 downto 0);
28        address : in std_logic_vector(31 downto 2);
29        data_write : in std_logic_vector(31 downto 0);
30        data_read : out std_logic_vector(31 downto 0));
31end; --entity ram
32
33architecture logic of ram is
34   constant ADDRESS_WIDTH : natural := 13;
35begin
36
37   generic_ram:
38   if memory_type /= "ALTERA_LPM" generate
39   begin
40   --Simulate a synchronous RAM
41   ram_proc: process(clk, enable, write_byte_enable,
42         address, data_write) --mem_write, mem_sel
43      variable mem_size : natural := 2 ** ADDRESS_WIDTH;
44      variable data : std_logic_vector(31 downto 0);
45      subtype word is std_logic_vector(data_write'length-1 downto 0);
46      type storage_array is
47         array(natural range 0 to mem_size/4 - 1) of word;
48      variable storage : storage_array;
49      variable index : natural := 0;
50      file load_file : text open read_mode is "code.txt";
51      variable hex_file_line : line;
52   begin
53
54      --Load in the ram executable image
55      if index = 0 then
56         while not endfile(load_file) loop
57--The following two lines had to be commented out for synthesis
58            readline(load_file, hex_file_line);
59            hread(hex_file_line, data);
60            storage(index) := data;
61            index := index + 1;
62         end loop;
63      end if;
64
65      if rising_edge(clk) then
66         index := conv_integer(address(ADDRESS_WIDTH-1 downto 2));
67         data := storage(index);
68
69         if enable = '1' then
70            if write_byte_enable(0) = '1' then
71               data(7 downto 0) := data_write(7 downto 0);
72            end if;
73            if write_byte_enable(1) = '1' then
74               data(15 downto 8) := data_write(15 downto 8);
75            end if;
76            if write_byte_enable(2) = '1' then
77               data(23 downto 16) := data_write(23 downto 16);
78            end if;
79            if write_byte_enable(3) = '1' then
80               data(31 downto 24) := data_write(31 downto 24);
81            end if;
82         end if;
83      
84         if write_byte_enable /= "0000" then
85            storage(index) := data;
86         end if;
87      end if;
88
89      data_read <= data;
90   end process;
91   end generate; --generic_ram
92
93
94   altera_ram:
95   if memory_type = "ALTERA_LPM" generate
96      signal byte_we : std_logic_vector(3 downto 0);
97   begin
98      byte_we <= write_byte_enable when enable = '1' else "0000";
99      lpm_ram_io_component0 : lpm_ram_dq
100         GENERIC MAP (
101            intended_device_family => "UNUSED",
102            lpm_width => 8,
103            lpm_widthad => ADDRESS_WIDTH-2,
104            lpm_indata => "REGISTERED",
105            lpm_address_control => "REGISTERED",
106            lpm_outdata => "UNREGISTERED",
107            lpm_file => "code0.hex",
108            use_eab => "ON",
109            lpm_type => "LPM_RAM_DQ")
110         PORT MAP (
111            data => data_write(31 downto 24),
112            address => address(ADDRESS_WIDTH-1 downto 2),
113            inclock => clk,
114            we => byte_we(3),
115            q => data_read(31 downto 24));
116
117      lpm_ram_io_component1 : lpm_ram_dq
118         GENERIC MAP (
119            intended_device_family => "UNUSED",
120            lpm_width => 8,
121            lpm_widthad => ADDRESS_WIDTH-2,
122            lpm_indata => "REGISTERED",
123            lpm_address_control => "REGISTERED",
124            lpm_outdata => "UNREGISTERED",
125            lpm_file => "code1.hex",
126            use_eab => "ON",
127            lpm_type => "LPM_RAM_DQ")
128         PORT MAP (
129            data => data_write(23 downto 16),
130            address => address(ADDRESS_WIDTH-1 downto 2),
131            inclock => clk,
132            we => byte_we(2),
133            q => data_read(23 downto 16));
134
135      lpm_ram_io_component2 : lpm_ram_dq
136         GENERIC MAP (
137            intended_device_family => "UNUSED",
138            lpm_width => 8,
139            lpm_widthad => ADDRESS_WIDTH-2,
140            lpm_indata => "REGISTERED",
141            lpm_address_control => "REGISTERED",
142            lpm_outdata => "UNREGISTERED",
143            lpm_file => "code2.hex",
144            use_eab => "ON",
145            lpm_type => "LPM_RAM_DQ")
146         PORT MAP (
147            data => data_write(15 downto 8),
148            address => address(ADDRESS_WIDTH-1 downto 2),
149            inclock => clk,
150            we => byte_we(1),
151            q => data_read(15 downto 8));
152
153      lpm_ram_io_component3 : lpm_ram_dq
154         GENERIC MAP (
155            intended_device_family => "UNUSED",
156            lpm_width => 8,
157            lpm_widthad => ADDRESS_WIDTH-2,
158            lpm_indata => "REGISTERED",
159            lpm_address_control => "REGISTERED",
160            lpm_outdata => "UNREGISTERED",
161            lpm_file => "code3.hex",
162            use_eab => "ON",
163            lpm_type => "LPM_RAM_DQ")
164         PORT MAP (
165            data => data_write(7 downto 0),
166            address => address(ADDRESS_WIDTH-1 downto 2),
167            inclock => clk,
168            we => byte_we(0),
169            q => data_read(7 downto 0));
170
171   end generate; --altera_ram
172
173
174   --For XILINX see ram_xilinx.vhd
175
176end; --architecture logic
177

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