Hardware Design: SIE
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| 1 | --------------------------------------------------------------------- |
| 2 | -- TITLE: Shifter Unit |
| 3 | -- AUTHOR: Steve Rhoads (rhoadss@yahoo.com) |
| 4 | -- Matthias Gruenewald |
| 5 | -- DATE CREATED: 2/2/01 |
| 6 | -- FILENAME: shifter.vhd |
| 7 | -- PROJECT: Plasma CPU core |
| 8 | -- COPYRIGHT: Software placed into the public domain by the author. |
| 9 | -- Software 'as is' without warranty. Author liable for nothing. |
| 10 | -- DESCRIPTION: |
| 11 | -- Implements the 32-bit shifter unit. |
| 12 | --------------------------------------------------------------------- |
| 13 | library ieee; |
| 14 | use ieee.std_logic_1164.all; |
| 15 | use work.mlite_pack.all; |
| 16 | |
| 17 | entity shifter is |
| 18 | generic(shifter_type : string := "DEFAULT"); |
| 19 | port(value : in std_logic_vector(31 downto 0); |
| 20 | shift_amount : in std_logic_vector(4 downto 0); |
| 21 | shift_func : in shift_function_type; |
| 22 | c_shift : out std_logic_vector(31 downto 0)); |
| 23 | end; --entity shifter |
| 24 | |
| 25 | architecture logic of shifter is |
| 26 | -- type shift_function_type is ( |
| 27 | -- shift_nothing, shift_left_unsigned, |
| 28 | -- shift_right_signed, shift_right_unsigned); |
| 29 | |
| 30 | signal shift1L, shift2L, shift4L, shift8L, shift16L : std_logic_vector(31 downto 0); |
| 31 | signal shift1R, shift2R, shift4R, shift8R, shift16R : std_logic_vector(31 downto 0); |
| 32 | signal fills : std_logic_vector(31 downto 16); |
| 33 | |
| 34 | begin |
| 35 | fills <= "1111111111111111" when shift_func = SHIFT_RIGHT_SIGNED |
| 36 | and value(31) = '1' |
| 37 | else "0000000000000000"; |
| 38 | shift1L <= value(30 downto 0) & '0' when shift_amount(0) = '1' else value; |
| 39 | shift2L <= shift1L(29 downto 0) & "00" when shift_amount(1) = '1' else shift1L; |
| 40 | shift4L <= shift2L(27 downto 0) & "0000" when shift_amount(2) = '1' else shift2L; |
| 41 | shift8L <= shift4L(23 downto 0) & "00000000" when shift_amount(3) = '1' else shift4L; |
| 42 | shift16L <= shift8L(15 downto 0) & ZERO(15 downto 0) when shift_amount(4) = '1' else shift8L; |
| 43 | |
| 44 | shift1R <= fills(31) & value(31 downto 1) when shift_amount(0) = '1' else value; |
| 45 | shift2R <= fills(31 downto 30) & shift1R(31 downto 2) when shift_amount(1) = '1' else shift1R; |
| 46 | shift4R <= fills(31 downto 28) & shift2R(31 downto 4) when shift_amount(2) = '1' else shift2R; |
| 47 | shift8R <= fills(31 downto 24) & shift4R(31 downto 8) when shift_amount(3) = '1' else shift4R; |
| 48 | shift16R <= fills(31 downto 16) & shift8R(31 downto 16) when shift_amount(4) = '1' else shift8R; |
| 49 | |
| 50 | GENERIC_SHIFTER: if shifter_type = "DEFAULT" generate |
| 51 | c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else |
| 52 | shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or |
| 53 | shift_func = SHIFT_RIGHT_SIGNED else |
| 54 | ZERO; |
| 55 | end generate; |
| 56 | |
| 57 | AREA_OPTIMIZED_SHIFTER: if shifter_type /= "DEFAULT" generate |
| 58 | c_shift <= shift16L when shift_func = SHIFT_LEFT_UNSIGNED else (others => 'Z'); |
| 59 | c_shift <= shift16R when shift_func = SHIFT_RIGHT_UNSIGNED or |
| 60 | shift_func = SHIFT_RIGHT_SIGNED else (others => 'Z'); |
| 61 | c_shift <= ZERO when shift_func = SHIFT_NOTHING else (others => 'Z'); |
| 62 | end generate; |
| 63 | |
| 64 | end; --architecture logic |
| 65 | |
| 66 |
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